D12363VTE33 Renesas Electronics America, D12363VTE33 Datasheet - Page 706

• Manufacturer Part Number: D12363VTE33
• Description: MCU 3V 0K 120-TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2300r

Specifications of D12363VTE33

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 33MHz
• Connectivity: I²C, IrDA, SCI, SmartCard
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 84
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 10x10b, D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 120-TQFP, 120-VQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -
• Other names: HD6412363VTE33; HD6412363VTE33

Section 15 I
15.4.3
In master receive mode, the master device outputs the receive clock, receives data from the slave
device, and returns an acknowledge signal. For master receive mode operation timing, refer to
figures 15.7 and 15.8. The reception procedure and operations in master receive mode are shown
below.
1. Clear the TEND bit in ICSR to 0, then clear the TRS bit in ICCRA to 0 to switch from master
2. When ICDRR is read (dummy data read), reception is started, and the receive clock is output,
3. After the reception of first frame data is completed, the RDRF bit in ICST is set to 1 at the rise
4. The continuous reception is performed by reading ICDRR and clearing RDRF to 0 every time
5. If next frame is the last receive data, set the RCVD bit in ICCR1 to 1 before reading ICDRR.
6. When the RDRF bit is set to 1 at rise of the 9th receive clock pulse, read ICDRR. Then, clear
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REJ09B0050-0600
(master output)
(master output)
(slave output)
transmit mode to master receive mode. Then, clear the TDRE bit to 0.
and data received, in synchronization with the internal clock. The master device outputs the
level specified by ACKBT in ICIER to SDA, at the 9th receive clock pulse.
of 9th receive clock pulse. At this time, the received data is read by reading ICDRR.
RDRF is set. If 8th receive clock pulse falls after reading ICDRR by the other processing while
RDRF is 1, SCL is fixed low until ICDRR is read.
This enables the issuance of the stop condition after the next reception.
RCVD.
processing
SCL
ICDRS
SDA
SDA
ICDRT
TDRE
TEND
User
Master Receive Operation
2
C Bus Interface2 (IIC2) (Option)
[5] Write data to ICDRT. Clear TDRE.
Figure 15.6 Master Transmit Mode Operation Timing 2
A
9
Bit 7
1
Bit 6
2
Bit 5
3
Data n
Data n
Bit 4
4
Bit 3
5
Bit 2
6
[6] Issue stop condition. Clear TEND.
Bit 1
7
Bit 0
8
[7] Set slave receive mode
A/
9