D12363VTE33 Renesas Electronics America, D12363VTE33 Datasheet - Page 256

• Manufacturer Part Number: D12363VTE33
• Description: MCU 3V 0K 120-TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2300r

Specifications of D12363VTE33

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 33MHz
• Connectivity: I²C, IrDA, SCI, SmartCard
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 84
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 10x10b, D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 120-TQFP, 120-VQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -
• Other names: HD6412363VTE33; HD6412363VTE33

Section 6 Bus Controller (BSC)
Idle Cycle in Case of DRAM Space Access after Normal Space Access: In a DRAM space
access following a normal space access, the settings of bits ICIS2, ICIS1, ICIS0, and IDLC in
BCR are valid. However, in the case of consecutive reads in different areas, for example, if the
second read is a full access to DRAM space, only a T
timing in this case is shown in figure 6.48.
Rev.6.00 Mar. 18, 2009 Page 196 of 980
REJ09B0050-0600
Address bus
CS (area A)
CS (area B)
Figure 6.47 Relationship between Chip Select (CS) and Read (RD)
RD
Figure 6.48 Example of DRAM Full Access after External Read
Overlap period between CS (area B)
and RD may occur
φ
Address bus
(a) No idle cycle insertion
Data bus
T
(ICIS1 = 0)
1
Bus cycle A
RD
φ
T
2
T
3
Bus cycle B
T
T
1
1
External read
T
T
2
2
(CAST = 0)
Address bus
CS (area A)
CS (area B)
T
3
p
T
RD
cycle is inserted, and a T
p
φ
DRAM space read
T
r
T
(b) Idle cycle insertion
1
Bus cycle A
(ICIS1 = 1, initial value)
T
T
c1
2
T
T
3
c2
Idle cycle
T
i
Bus cycle B
i
cycle is not. The
T
1
T
2