D12363VTE33 Renesas Electronics America, D12363VTE33 Datasheet - Page 693

• Manufacturer Part Number: D12363VTE33
• Description: MCU 3V 0K 120-TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2300r

Specifications of D12363VTE33

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 33MHz
• Connectivity: I²C, IrDA, SCI, SmartCard
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 84
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 10x10b, D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 120-TQFP, 120-VQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -
• Other names: HD6412363VTE33; HD6412363VTE33

15.3.1
ICCRA is an 8-bit readable/writable register that enables or disables the I
transmission or reception, and selects master or slave mode, transmission or reception, and transfer
clock frequency in master mode.
Bit Bit Name
7
6
5
4
3
2
1
0
ICE
RCVD
MST
TRS
CKS3
CKS2
CKS1
CKS0
I
2
C Bus Control Register A (ICCRA)
Initial Value R/W
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Description
I
0: This module is halted.
1: This bit is enabled for transfer operations. (SCL and SDA
Reception Disable
This bit enables or disables the next operation when TRS is
0 and ICDRR is read.
0: Enables next reception
1: Disables next reception
Master/Slave Select
Transmit/Receive Select
When arbitration is lost in master mode, MST and TRS are
both reset by hardware, causing a transition to slave
receive mode. Modification of the TRS bit should be made
between transfer frames. In addition, TRS is set to 1
automatically in slave receive mode when the seventh bit of
the start condition matches the slave address set in SAR
and the eighth bit is set to 1.
Operating modes are described below according to MST
and TRS combination.
00: Slave receive mode
01: Slave transmit mode
10: Master receive mode
11: Master transmit mode
Transfer clock select 3 to 0
In master mode, these bits should be set according to the
necessary transfer rate. In slave mode, they are used to
secure the data setup time in transmit mode. The data
setup time is 10 tcyc when CKS3 is cleared to 0; 20 tcyc
when CKS3 is set to 1.
2
C Bus Interface Enable
pins are bus drive state.)
Section 15 I
Rev.6.00 Mar. 18, 2009 Page 633 of 980
2
C Bus Interface2 (IIC2) (Option)
2
C bus interface, controls
REJ09B0050-0600