D12363VTE33 Renesas Electronics America, D12363VTE33 Datasheet - Page 197

MCU 3V 0K 120-TQFP

D12363VTE33

Manufacturer Part Number
D12363VTE33
Description
MCU 3V 0K 120-TQFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2300r
Datasheet

Specifications of D12363VTE33

Core Processor
H8S/2000
Core Size
16-Bit
Speed
33MHz
Connectivity
I²C, IrDA, SCI, SmartCard
Peripherals
DMA, POR, PWM, WDT
Number Of I /o
84
Program Memory Type
ROMless
Ram Size
16K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 10x10b, D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
120-TQFP, 120-VQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Program Memory Size
-
Other names
HD6412363VTE33
HD6412363VTE33

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
D12363VTE33V
Manufacturer:
Renesas Electronics America
Quantity:
10 000
Bit
6
5
4 and
3
Bit Name
RCDM
DDS
Initial Value
0
0
All 0
R/W
R/W
R/W
R/W
Description
RAS Down Mode
When access to DRAM space is interrupted by
an access to normal space, an access to an
internal I/O register, etc., this bit selects whether
the RAS signal is held low while waiting for the
next DRAM access (RAS down mode), or is
driven high again (RAS up mode). The setting
of this bit is valid only when the BE bit is set to
1.
If this bit is cleared to 0 when set to 1 in the
RAS down state, the RAS down state is cleared
at that point, and RAS goes high.
0: RAS up mode selected for DRAM space
1: RAS down mode selected for DRAM space
DMAC Single Address Transfer Option
Selects whether full access is always performed
or burst access is enabled when DMAC single
address transfer is performed on the DRAM
When the BE bit is cleared to 0 in DRAMCR,
disabling DRAM burst access, DMAC single
address transfer is performed in full access
mode regardless of the setting of this bit.
This bit has no effect on other bus master
external accesses or DMAC dual address
transfers.
0: Full access is always executed
1: Burst access is enabled
Reserved
Though these bits can be read from or written
to, the write value should always be 0.
access
access
Rev.6.00 Mar. 18, 2009 Page 137 of 980
Section 6 Bus Controller (BSC)
REJ09B0050-0600

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