D12363VTE33 Renesas Electronics America, D12363VTE33 Datasheet - Page 622

MCU 3V 0K 120-TQFP

D12363VTE33

Manufacturer Part Number
D12363VTE33
Description
MCU 3V 0K 120-TQFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2300r
Datasheet

Specifications of D12363VTE33

Core Processor
H8S/2000
Core Size
16-Bit
Speed
33MHz
Connectivity
I²C, IrDA, SCI, SmartCard
Peripherals
DMA, POR, PWM, WDT
Number Of I /o
84
Program Memory Type
ROMless
Ram Size
16K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 10x10b, D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
120-TQFP, 120-VQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Program Memory Size
-
Other names
HD6412363VTE33
HD6412363VTE33

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
D12363VTE33V
Manufacturer:
Renesas Electronics America
Quantity:
10 000
Section 14 Serial Communication Interface (SCI, IrDA)
Notes: 1. Only 0 can be written, to clear the flag. Alternately, use the bit clear instruction to clear
Rev.6.00 Mar. 18, 2009 Page 562 of 980
REJ09B0050-0600
Bit
2
1
0
2. etu: Elementary Time Unit: (time for transfer of 1 bit)
Bit Name
TEND
MPB
MPBT
the flag.
Initial Value
1
0
0
R/W
R
R
R/W
Description
Transmit End
This bit is set to 1 when no error signal has been
sent back from the receiving end and the next
transmit data is ready to be transferred to TDR.
[Setting conditions]
Timing to set this bit differs according to the
register settings.
GM = 0, BLK = 0: 2.5 etu*
GM = 0, BLK = 1: 1.5 etu*
GM = 1, BLK = 0: 1.0 etu*
GM = 1, BLK = 1: 1.0 etu*
Multiprocessor Bit
This bit is not used in Smart Card interface
mode.
Multiprocessor Bit Transfer
Write 0 to this bit in Smart Card interface mode.
[Clearing conditions]
When the TE bit in SCR is 0 and the ERS bit
is also 0
If the ERS bit is 0 and the TDRE bit is 1 after
the specified interval after transmission of 1-
byte data
When 0 is written to TEND after reading
TEND = 1
When the DMAC or DTC is activated by a TXI
interrupt and writes data to TDR
2
2
2
2
after transmission
after transmission
after transmission
after transmission

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