D12363VTE33 Renesas Electronics America, D12363VTE33 Datasheet - Page 33

• Manufacturer Part Number: D12363VTE33
• Description: MCU 3V 0K 120-TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2300r

Specifications of D12363VTE33

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 33MHz
• Connectivity: I²C, IrDA, SCI, SmartCard
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 84
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 10x10b, D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 120-TQFP, 120-VQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -
• Other names: HD6412363VTE33; HD6412363VTE33

12.3 Register Descriptions ........................................................................................................ 509
12.4 Operation........................................................................................................................... 515
12.5 Operation Timing.............................................................................................................. 516
12.6 Operation with Cascaded Connection ............................................................................... 520
12.7 Interrupts ........................................................................................................................... 521
12.8 Usage Notes ...................................................................................................................... 522
Section 13 Watchdog Timer
13.1 Features ............................................................................................................................. 529
13.2 Input/Output Pin................................................................................................................ 530
13.3 Register Descriptions ........................................................................................................ 531
13.4 Operation........................................................................................................................... 534
12.3.1 Timer Counter (TCNT)........................................................................................ 509
12.3.2 Time Constant Register A (TCORA)................................................................... 510
12.3.3 Time Constant Register B (TCORB) ................................................................... 510
12.3.4 Timer Control Register (TCR) ............................................................................ 510
12.3.5 Timer Control/Status Register (TCSR)................................................................ 512
12.4.1 Pulse Output......................................................................................................... 515
12.5.1 TCNT Incrementation Timing ............................................................................. 516
12.5.2 Timing of CMFA and CMFB Setting when Compare-Match Occurs ................. 517
12.5.3 Timing of Timer Output when Compare-Match Occurs...................................... 518
12.5.4 Timing of Compare Match Clear ......................................................................... 518
12.5.5 Timing of TCNT External Reset.......................................................................... 519
12.5.6 Timing of Overflow Flag (OVF) Setting ............................................................. 519
12.6.1 16-Bit Counter Mode ........................................................................................... 520
12.6.2 Compare Match Count Mode............................................................................... 520
12.7.1 Interrupt Sources and DTC Activation ................................................................ 521
12.7.2 A/D Converter Activation.................................................................................... 521
12.8.1 Contention between TCNT Write and Clear........................................................ 522
12.8.2 Contention between TCNT Write and Increment ................................................ 523
12.8.3 Contention between TCOR Write and Compare Match ...................................... 524
12.8.4 Contention between Compare Matches A and B ................................................. 525
12.8.5 Switching of Internal Clocks and TCNT Operation............................................. 525
12.8.6 Mode Setting with Cascaded Connection ............................................................ 527
12.8.7 Interrupts in Module Stop Mode .......................................................................... 527
13.3.1 Timer Counter (TCNT)........................................................................................ 531
13.3.2 Timer Control/Status Register (TCSR)................................................................ 531
13.3.3 Reset Control/Status Register (RSTCSR) ............................................................ 533
13.4.1 Watchdog Timer Mode ........................................................................................ 534
13.4.2 Interval Timer Mode ............................................................................................ 535
............................................................................................. 529
Rev.6.00 Mar. 18, 2009 Page xxxi of lviii
REJ09B0050-0600