PEB2254H-V14 Infineon Technologies, PEB2254H-V14 Datasheet - Page 120

• Manufacturer Part Number: PEB2254H-V14
• Manufacturer: Infineon Technologies

Specifications of PEB2254H-V14

• Operating Supply Voltage (typ): 5V
• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Compliant

AIS…
LFA…
Semiconductor Group
Recovery:
Analog interface: The bit will be reset when the incoming signal has
transitions with signal levels greater than the programmed receive
input level (LIM1.RIL2-0) for at least M pulse periods defined by
register PCR in the PCD time interval.
Digital interface: The bit will be reset when the incoming data stream
contains at least M ones defined by register PCR in the PCD time
interval.
With the rising edge of this bit an interrupt status bit (ISR2.LOS) will
be set. For additionally recovery conditions refer also to register
LIM2.LOS2/1.
The bit will also be set during alarm simulation and reset if FMR0.SIM
is cleared and no alarm condition exists.
Alarm Indication Signal
The function of this bit is determined by FMR0.ALM.
FMR0.ALM = 0:
FMR0.ALM = 1:
The bit will also be set during alarm simulation and reset if FMR0.SIM
is cleared and no alarm condition exists.
With the rising edge of this bit an interrupt status bit (ISR2.AIS) will be
set.
Loss of Frame Alignment
This bit is set after detecting 3 or 4 consecutive incorrect FAS words
or 3 or 4 consecutive incorrect service words (can be disabled). With
the rising edge of this bit an interrupt status bit (ISR2.LFA) will be set.
The specification of the loss of sync conditions is done via bits
RC1.SWD and RC1.ASY4. After loss of synchronization, the frame
aligner will resynchronize automatically.
This bit is set when two or less zeros in the
received bit stream are detected in a time interval
of 250 s and the FALC54 is in the asynchronous
state (FRS0.LFA = 1). The bit will be reset when
no alarm condition is detected (ETSI).
This bit is set when the incoming signal has two or
less Zeros in each of two consecutive double
frame periods(512 bits). This bit will be cleared
when each of two consecutive doubleframe
periods contain three or more Zeros or when the
frame alignment signal FAS has been found.
(ITU-T: G.775)
120
Operational Description E1
PEB 2254
11.96