PEB2254H-V14 Infineon Technologies, PEB2254H-V14 Datasheet - Page 84

• Manufacturer Part Number: PEB2254H-V14
• Manufacturer: Infineon Technologies

Specifications of PEB2254H-V14

• Operating Supply Voltage (typ): 5V
• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Compliant

XRES…
XHF…
XTF…
XME…
SRES…
Semiconductor Group
Transmitter Reset
The transmit framer and transmit line interface excluding the system
clock generator and the pulse shaper will be reset. However the
contents of the control registers will not be deleted.
Transmit HDLC Frame
After having written up to 32 bytes to the XFIFO, this command
initiates the transmission of a HDLC frame.
Transmit Transparent Frame
Initiates the transmission of a transparent frame without HDLC
framing.
Transmit Message End
Indicates that the data block written last to the transmit FIFO
completes the current frame. The FALC54 can terminate the
transmission operation properly by appending the CRC and the
closing flag sequence to the data.
Signaling Transmitter Reset
The transmitter of the signaling controller will be reset. XFIFO is
cleared of any data and an abort sequence (seven 1's) followed by
interframe time fill is transmitted. In response to XRES a XPR
interrupt is generated.
This command can be used by the CPU to abort a frame currently in
transmission.
Note: The maximum time between writing to the CMDR register and
the execution of the command depends on FMR1.IMOD. If
FMR1.IMOD is set it takes 10 SCLKX cycles and 5 SCLKX
cycles if FMR1.IMOD is cleared. Therefore, if the CPU
operates with a very high clock rate in comparison with the
FALC's clock, it is recommended that bit SIS.CEC should be
checked before writing to the CMDR register to avoid any loss
of commands.
84
Operational Description E1
PEB 2254
11.96