PEB2254H-V14 Infineon Technologies, PEB2254H-V14 Datasheet - Page 182

• Manufacturer Part Number: PEB2254H-V14
• Manufacturer: Infineon Technologies

Specifications of PEB2254H-V14

• Operating Supply Voltage (typ): 5V
• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Compliant

PEB 2254
General Functions and Device Architecture T1
5.1.2
Transmit Path
The inverse functions are performed for the transmit direction.
The PCM data is received from the system internal highway at port XDI with 2048 kbit/s
or 4096 kbit/s. The channel assignment is equivalent to the receive direction. All
unequipped (idle) time-slots will be ignored.
The contents of selectable channels (time-slots) can be overwritten by the pattern
defined via register IDLE. The selection of “idle channels” is done by programming the
three-byte registers ICB1 … ICB3.
Internal multiplexing of (speech) data and signaling data can be disabled on a per
channel basis (Clear Channel Capability). This is also valid when using the internal
signaling controller.
Latching of data is controlled by the System Clock (SCLKX) and the Synchronous Pulse
(SYPXQ) in conjunction with the programmed offset values for the Transmit
Time-slot/Clock-slot Counters.
Transmit Signaling Controller
Similar to the receive signaling controller the same signaling methods and the same
time-slot assignment are provided. The signaling information has to be written in the
Transmit FIFO (XFIFO). With a Transmit Frame command the signaling information will
be sent in the corresponding signaling bit positions. The signaling will be internally
multiplexed with the data at port XDI.
If the transparent mode is selected, the FALC54 supports the continuous transmission of
the contents of the transmit FIFO. The cyclic transmission continuous until the
Transmitter Reset command (CMDR.SRES) is issued or CMDR.XREP is reset.
In case of CCS the signaling procedure HDLC/SDLC is supported with generation of
Preambles and FLAGs, CRC generation and bit-stuffing. For HDLC frames, the address
and the control fields have to be entered in the XFIFO as well.
Operating in HDLC or BOM mode “flags” or “idle” may be transmitted as interframe
timefill.
Semiconductor Group
182
11.96