PEB2254H-V14 Infineon Technologies, PEB2254H-V14 Datasheet - Page 52

• Manufacturer Part Number: PEB2254H-V14
• Manufacturer: Infineon Technologies

Specifications of PEB2254H-V14

• Operating Supply Voltage (typ): 5V
• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Compliant

PEB 2254
General Functions and Device Architecture E1
The multiframe synchronous state is established after detecting two correct multiframe
alignment signals at an interval of n
2 ms (n = 1, 2, 3 …). The Loss of multiframe
alignment flag FRS0.LMFA will be reset. Additionally an interrupt status multiframe
alignment recovery bit ISR2.MFAR is generated with the falling edge of bit FRS0.LMFA.
Automatic Force Resynchronization
In addition, a search for Doubleframe alignment is automatically initiated if two
multiframe pattern with a distance of n
2 ms have not been found within a time interval
of 8 ms after doubleframe alignment has been regained (bit FMR1.AFR). The research
for frame alignment will be started just after the previous frame alignment signal.
Floating Multiframe Alignment Window
After reaching doubleframe synchronization a 8 ms timer is started. If a multiframe
alignment signal is found during the 8 ms time interval the internal timer will be reset to
remaining 6 ms in order to find the next multiframe signal within this time. If the
multiframe signal is not found for a second time an interrupt status ISR0. T8MS will be
provided. This interrupt will usually occur every 8 ms until multiframe synchronization is
achieved.
CRC4 Performance Monitoring
In the synchronous state checking of multiframe pattern is disabled. However, with bit
FMR2.ALMF an automatic multiframe resynchronization mode can be activated. If 915
out of 1000 errored CRC submultiframes are found then a false frame alignment will be
assumed and a search for double- and multiframe pattern is initiated. The new search for
frame alignment will be started just after the previous basic frame alignment signal. The
internal CRC4 resynchronization counter will be reset when the multiframe
synchronization has been regained.
Modified CRC4 Multiframe Alignment Algorithm
The modified CRC4 multiframe alignment algorithm allows an automatic interworking
between framers with and without a CRC4 capability. The interworking is realized as it is
described in ITU-T G.706 Appendix B.
If doubleframe synchronization is consistently present but CRC4 multiframe alignment is
not achieved within 400 ms it is assumed that the distant end is initialized to doubleframe
format. The CRC4 - Non CRC4 interworking is enabled via FMR2.RFS1/0 = 11 and is
activated only if the receiver has lost its synchronization. If doubleframe alignment (basic
frame alignment) is established a 400 ms timer and searching for multiframe alignment
will be started. A research for basic frame alignment will be initiated if the CRC4
multiframe synchronization could not be achieved within 8 ms and will be started just
after the previous frame alignment signal. The research of the basic frame alignment is
done in parallel and is independent of the synchronization procedure of the primary basic
Semiconductor Group
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