PEB2254H-V14 Infineon Technologies, PEB2254H-V14 Datasheet - Page 281

• Manufacturer Part Number: PEB2254H-V14
• Manufacturer: Infineon Technologies

Specifications of PEB2254H-V14

• Operating Supply Voltage (typ): 5V
• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Compliant

ISF…
RMB…
RSC…
CRC6…
PDEN…
RPF…
Interrupt Status Register 1 (Read)
ISR1
All bits are reset when ISR1 is read.
Semiconductor Group
7
CASE
are valid and can be read by the CPU.
Incorrect Sync Format
The FALC54 could not detect eight consecutive one’s within 32 bits
in BOM mode. Only valid if BOM receiver has been activated.
Receive Multiframe Begin
This bit is set with the beginning of a received multiframe of the
receive line timing.
Received Signaling Information Changed
This bit is set with the updating of a received signaling information in
registers RS1-6 resp. RS1-12. If the last received signaling
information changed from the previous received updating is started.
This interrupt will only occur in the synchronous state. The registers
RS1-6 /12 should be read within the next 1.5 / 3 ms otherwise the
contents may be lost.
Receive CRC6 Error
0…
1…
Pulse Density violation
The pulse density violation of the received data stream defined by
ANSI T1. 403 is violated. More than 15 consectuive zeros or less than
N ones in each and every time window of 8(N+1) data bits (N=23) are
detected. If IPC.SCI is set high this interrupt status bit will be activated
with every change of state of FRS1.PDEN.
Receive Pool Full
32 bytes of a frame have arrived in the receive FIFO. The frame is not
yet completely received.
RDO
• RAL1
• RSIS - bits 3-1
No CRC6 error occurs.
The CRC6 check of the last received multiframe failed.
ALLS
XDU
281
XMB
Operational Description T1
XLSC
0
XPR
PEB 2254
(69)
11.96