PEB2254H-V14 Infineon Technologies, PEB2254H-V14 Datasheet - Page 17

• Manufacturer Part Number: PEB2254H-V14
• Manufacturer: Infineon Technologies

Specifications of PEB2254H-V14

• Operating Supply Voltage (typ): 5V
• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Compliant

Pin Definitions and Function (cont’d)
Pin No.
60
72
57
71
Semiconductor Group
Symbol
SYNC
RCLK
RDO
RFSP
Input (I)
Output (O)
I
O
O
O
Function
Clock Synchronization
If a clock is detected at the SYNC pin the
FALC54 synchronizes to this 2.048 MHz clock.
This pin has to be connected to
is supplied.
Receive Clock
Extracted from the incoming data pulses
Clock frequency: 2048 kHz
If LIM0.ELOS is set, the RCLK is set high in
case of loss of signal (FRS0.LOS=1).
Receive Data Out
Received data which is sent to the system
internal highway with 4096 kbit/s or 2048 kbit/s
(bit FMR1.IMOD). In 4096 kbit/s mode data is
shifted out in that channel phase which is
selected by register RC0.SICS.The other
channel phase is set in tri-state. Clocking off
data is done with the falling edge of SCLKR.
The delay between the beginning of time-slot 0
and the initial edge of SCLKR (after SYPR goes
active) is determined by the values of Receive
Time-slot Offset RC1.RTO5 … 0, Receive
Clock-slot Offset RC0.RCO2 … 0 and
RC0.RCOS.
Receive Frame Synchronous Pulse (active
low)
Framing pulse derived from the received PCM
route signal. During loss of synchronization (bit
FRS0.LFA), this pulse is suppressed (not
influenced during alarm simulation).
Pulse frequency: 8 kHz
Pulse width: 488 ns
Setting of FMR3.CFRZ the status of the CAS
synchronizer will be output via this pin. It is set
high if the CAS controller is in the asynchronous
state.
17
General Features E1
V
SS
if no clock
PEB 2254
11.96