PEB2254H-V14 Infineon Technologies, PEB2254H-V14 Datasheet - Page 253

• Manufacturer Part Number: PEB2254H-V14
• Manufacturer: Infineon Technologies

Specifications of PEB2254H-V14

• Operating Supply Voltage (typ): 5V
• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Compliant

RTO5…RTO0…Receive Time-Slot Offset
Transmit Pulse-Mask 2…0 (Read/Write)
Value after RESET: 9C
XPM0
Semiconductor Group
7
XP12
F4:
F12: – FMR0.SRAF = 0: bit2 = 0 in every speech channel per frame.
ESF: – FMR0.SRAF = 0: pattern ‘1111 1111 0000 0000…’ in data
F72: bit2 = 0 in every speech channel per frame.
Release
The alarm will be reset when above conditions are no longer
detected.
RRAM = 1
Detection
F4:
F12: – FMR0.SRAF = 0: bit 2 = 0 in 255 consecutive speech
ESF: – FMR0.SRAF = 0: pattern ‘1111 1111 0000 0000…’ in data
F72: bit 2 = 0 in 255 consecutive speech channels.
Release
Depending on the selected multiframe format the alarm will be reset
when FALC54 does not detect
– the ‘bit 2 = 0’ condition for three consecutive pulseframes
– the ‘FS bit’ condition for three consecutive multiframes (F12),
– the ‘DL pattern’ for three times in a row (ESF).
Initial value loaded into the receive time-slot counter at the trigger
edge of SCLKR when the synchronous pulse at port SYPR is active
(see figure 56).
XP11
(all formats if selected),
H
bit2 = 0 in every speech channel per frame.
– FMR0.SRAF = 1: S-bit of frame 12 is forced to ‘1’
– FMR0.SRAF = 1: bit2 = 0 in every speech channel
bit2 = 0 in 255 consecutive speech channels.
– FMR0.SRAF = 1: S-bit of frame 12 is forced to ‘1’
– FMR0.SRAF = 1: bit 2 = 0 in 255 consecutive speech
, 03
link channel
channels.
link channel
channels
XP10
H
, 00
H
XP04
253
XP03
XP02
Operational Description T1
XP01
0
XP00
PEB 2254
(24)
11.96