PEB2254H-V14 Infineon Technologies, PEB2254H-V14 Datasheet - Page 267

• Manufacturer Part Number: PEB2254H-V14
• Manufacturer: Infineon Technologies

Specifications of PEB2254H-V14

• Operating Supply Voltage (typ): 5V
• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Compliant

AIS…
LFA…
RRA…
Semiconductor Group
register PCR in the PCD time interval.
Digital interface: The bit will be reset when the incoming data stream
contains at least M ones defined by register PCR in the PCD time
interval.
With the rising edge of this bit an interrupt status bit (ISR2.LOS) will
be set. For additionally recovery conditions refer also to register
LIM2.LOS2/1.
The bit will be set during alarm simulation and reset if FRS2.ESC = 0,
3, 4, 7 and no alarm condition exists.
Alarm Indication Signal (Blue Alarm)
This bit is set when the conditions defined by bit FMR4.AIS3 are
detected. The flag stays active for at least one multiframe.
With the rising edge of this bit an interrupt status bit (ISR2.AIS) will be
set. It will be reset with the beginning of the next following multiframe
if no alarm condition is detected.
The bit will be set during alarm simulation and reset if FRS2.ESC = 0,
3, 4, 7 and no alarm condition exists.
Loss of Frame Alignment
The flag is set if pulseframe synchronization has been lost. The
conditions are specified via bit FMR4.SSC1/0. Setting this bit will
cause an interrupt status (ISR2.LFA).
The flag is cleared when synchronization has been regained.
Additionally interrupt status ISR2.FAR is set with clearing this bit.
Receive Remote Alarm (Yellow Alarm)
The flag is set after detecting remote alarm (yellow alarm). Conditions
for setting/resetting are defined by bit RC1.RRAM.
With the rising edge of this bit an interrupt status bit ISR2.RA will be
set.
With the falling edge of this bit an interrupt status bit ISR2.RAR will be
set.
The bit will be set during alarm simulation and reset if FRS2.ESC = 0,
3, 4, 7 and no alarm condition exists.
267
Operational Description T1
PEB 2254
11.96