PEB2254H-V14 Infineon Technologies, PEB2254H-V14 Datasheet - Page 282

• Manufacturer Part Number: PEB2254H-V14
• Manufacturer: Infineon Technologies

Specifications of PEB2254H-V14

• Operating Supply Voltage (typ): 5V
• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Compliant

If bit IPC.VIS is set to ‘1’, interrupt statuses in ISR1 may be flagged although they are
masked via register IMR1. However, these masked interrupt statuses neither generate a
signal on INT, nor are visible in register GIS.
CASE…
RDO…
ALLS…
XDU…
XMB…
Semiconductor Group
Transmit CAS Register Empty
In ESF and F12 format this bit is set with the beginning of a
transmitted multiframe related to the internal transmitter timing. In
F72 format this interrupt will occur every 12 frames to inform the user
that new bit robbing data has to written to XS1-6 registers. In ESF
format this interrupt will occur every 24 frames to write registers
XS1-12.
Receive Data Overflow
This interrupt status indicates that the CPU does not respond quickly
enough to an RPF or RME interrupt and that data in RFIFO has been
lost. Even when this interrupt status is generated, the frame continues
to be received when space in the RFIFO is available again.
Note: Whereas the bit RSIS.RDO in the frame status byte indicates
All Sent
This bit is set if the last bit of the current frame is completely sent out
and XFIFO is empty.
Transmit Data Underrun
Transmitted frame was terminated with an abort sequence because
no data was available for transmission in XFIFO and no XME was
issued.
Note: Transmitter and XFIFO are reset and deactivated if this
Transmit Multiframe Begin
This bit is set with the beginning of a transmitted multiframe related to
the internal transmitter timing.
whether an overflow occurred when receiving the frame
currently accessed in the RFIFO, the ISR1.RDO interrupt
status is generated as soon as an overflow occurs and does
not necessarily pertain to the frame currently accessed by the
processor.
condition occurs. They are re-activated not before this
interrupt status register has been read. Thus, XDU should not
be masked via register IMR1.
282
Operational Description T1
PEB 2254
11.96