PEB2254H-V14 Infineon Technologies, PEB2254H-V14 Datasheet - Page 90

• Manufacturer Part Number: PEB2254H-V14
• Manufacturer: Infineon Technologies

Specifications of PEB2254H-V14

• Operating Supply Voltage (typ): 5V
• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Compliant

RADD…
RCRC…
XCRC…
Preamble Register (Read/Write)
Value after RESET: 00
PRE
PRE0...PRE7...
Semiconductor Group
7
PRE7
Receive Address Pushed to RFIFO
If this bit is set to ‘1’, the received HDLC address information (1 or 2
bytes, depending on the address mode selected via MODE.MDS0) is
pushed to RFIFO. This function is applicable in non-auto mode.
Receive CRC ON/OFF
Only applicable in non-auto mode.
If this bit is set to ‘1’, the received CRC checksum will be written to
RFIFO (CRC-ITU-T: 2 bytes). The checksum, consisting of the 2 last
bytes in the received frame, is followed in the RFIFO by the status
information byte (contents of register RSIS). The received CRC
checksum will additionally be checked for correctness. If non-auto
mode is selected, the limits for “Valid Frame” check are modified
(refer to RSIS.VFR).
Transmit CRC ON/OFF
If this bit is set to ‘1’, the CRC checksum will not be generated
internally. It has to be written as the last two bytes in the transmit FIFO
(XFIFO). The transmitted frame will be closed automatically with a
closing flag.
Note: The FALC54 does not check whether the length of the frame,
Preamble Register
This register defines the pattern which is sent out during preamble
transmission (refer to register CCR3). LSB is sent first.
Note: It should be taken into consideration that Zero Bit Insertion is
H
i.e. the number of bytes to be transmitted makes sense or not.
disabled during preamble transmission.
90
Operational Description E1
0
PRE0
PEB 2254
(0B)
11.96