PEB2254H-V14 Infineon Technologies, PEB2254H-V14 Datasheet - Page 174

• Manufacturer Part Number: PEB2254H-V14
• Manufacturer: Infineon Technologies

Specifications of PEB2254H-V14

• Operating Supply Voltage (typ): 5V
• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Compliant

Table 14
Recommended Receiver Configuration Values
Parameter
R
t
R
Jitter free system clocks (16 MHz / 8 MHz / 4 MHz / 2 MHz and 8 kHz) are generated by
the internal PLL circuit DCO1. The DCO1 can work in two different modes:
• Slave mode
• Master mode
Loss of Signal Detection
There are different definitions for detecting Loss of Signal alarms (LOS) in the ITU-T
G.775 and AT&T TR 54016. The FALC54 covers all these standards. The LOS
indication is performed by generating an interrupt (if not masked) and activating a status
bit. Additionally a LOS status change interrupt is programmable via register IPC.SCI.
• Detection:
• Recovery:
Semiconductor Group
2
1
2
:
In Slave mode (LIM0.MAS = 0), the DCO1 will be synchronized on the recovered
route clock. In case of LOS the DCO1 switches automatically to Master mode.
In Master mode (LIM0.MAS = 1), the oscillator is in free running mode if pin SYNC is
connected to VSS. If there is a frequency of 1.544 MHz (LIM1.DCOC = 0) or 2.048
MHz (LIM1.DCOC = 1) at the SYNC input the DCO1 is then synchronized to this input.
An alarm will be generated if the incoming data stream has no pulses (no transitions)
for a certain number (N) of consecutive pulse periods. “No pulse” in the digital receive
interface means a logical zero on pins RDIP/RDIN/ROID. A pulse with an amplitude
less than Q dB below nominal is the criteria for “no pulse” in the analog receive
interface (LIM1.DRS=0). The receive signal level Q is programmable via three control
bits LIM1.RIL2-0 in a range of about 1400 to 200 mV differential voltage between pins
RL1/2. The number N can be set via a 8 bit register PCD. The contents of the PCD
register will be multiplied by 16, which results in the number of pulse periods, or better,
the time which has to suspend until the alarm has to be detected. The range results
therefore from 16 to 4096 pulse periods.
In general the recovery procedure starts after detecting a logical ‘one’ (digital receive
interface) or a pulse (analog receive interface) with an amplitude more than Q dB
(defined by LIM1.RIL2-0) of the nominal pulse. The value in the 8 bit register PCR
defines the number of pulses (1 to 255) to clear the LOS alarm. Additional recovery
conditions may be programmed by register LIM2.
( 2.5 %) [ ]
( 2.5 %) [ ]
t
1
General Functions and Device Architecture T1
174
DS1 (6 dB)
0
1 : 2
200
Characteristic Impedance 100
T1 (18 dB)
0
1 : 2
200
PEB 2254
11.96