PEB2254H-V14 Infineon Technologies, PEB2254H-V14 Datasheet - Page 187

• Manufacturer Part Number: PEB2254H-V14
• Manufacturer: Infineon Technologies

Specifications of PEB2254H-V14

• Operating Supply Voltage (typ): 5V
• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Compliant

PEB 2254
General Functions and Device Architecture T1
5.1.3
Additional Functions
Clear Channel Capability
For support of common T1 applications, clear channels can be specified via the 3-byte
register bank CCB1 … CCB3. In this mode the contents of selected channels will not be
overwritten by bit robbing and Zero Code Suppression (B7 stuffing) information.
Idle Code Insertion
In transmit direction, the contents of selectable channels can be overwritten by the
pattern defined via register IDLE. The selection of “idle channels” is done by
programming the three-byte registers ICB1 … ICB3.
Loop Up/Down Code Detection and Generation
The FALC54 detects a framed or unframed Loop Up/actuate (00001)- and
Down/deactuate (001) pattern with bit error rates as high as 1/100. Framing bits are
excluded from loop code detection. Status and interrupt-status bits will inform the user
whether Loop Up - or Loop Down code was detected.
In transmit direction replacing normal transmit data with Loop Up- or Loop Down code is
done via control bits. However framing pattern will overwrite the Loop code.
Transparent Mode
The described transparent modes are useful for loopbacks or for routing signaling
information through the system interface.
Setting bit FMR4.TM switches the FALC54 in transparent mode:
In receive direction all bits in F-bit position of the incoming multiframe are forwarded to
RDO and inserted in the FS/DL time-slot. In asynchronous state the received data can
be transparently switched through if bit FMR2.DAIS is set. Bit RDCF (bit 1 of FS/DL
time-slot) indicates a DL bit.
In transmit direction bit 8 of the FS/DL time-slot from the system internal highway (XDI)
is inserted in the F-bit position of the outgoing frame. For complete transparency the
internal signaling controller and Line Loop Back has to be disabled and “Clear Channels”
have to be defined via registers CCB1 3.
Pulse Density Detection
The FALC54 examines the receive data stream on the pulse density requirement which
is defined by ANSI T1. 403. More than 15 consecutive zeros or less than N ones in each
and every time window of 8(N+1) data bits where N=23 will be detected. Violations of
these rules are indicated by setting the status bit FRS1.PDEN and the interrupt status bit
Semiconductor Group
187
11.96