PEB2254H-V14 Infineon Technologies, PEB2254H-V14 Datasheet - Page 198

• Manufacturer Part Number: PEB2254H-V14
• Manufacturer: Infineon Technologies

Specifications of PEB2254H-V14

• Operating Supply Voltage (typ): 5V
• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Compliant

CRC6 Alarm Interrupt
As an extension of the CRC6 checking algorithm the occurrence of a received CRC6
error may set an interrupt status.
The CRC6 checking algorithm is enabled via bit FMR1.CRC. If not enabled, all check
bits in the transmit direction are set to ‘1’.
Remote alarm (yellow alarm) is indicated by the periodical pattern ‘1111 1111 0000 0000
…’ in the DL bits.
All signaling schemes are applicable for this multiframing structure. For external access
to the DL bits, refer to section General.
Synchronization Procedure
For multiframe synchronization the FAS bits are observed. Synchronous state is
reached if at least one framing candidate is definitely found, or the synchronizer is forced
to lock onto the next available candidate (FMR0.FRS).
In the synchronous state the framing bits (FAS bits) are observed. Two errors within
4/5/6 framing bits or two or more erroneous framing bits within one ESF multiframe will
lead to the asynchronous state.
There are two multiframe synchronization modes selectable via FMR2.MCSP
• FMR2.MCSP = 0 : In the synchronous state, the setting of FMR0.FRS or FMR0.EXLS
• FMR2.MCSP = 1 : This mode has been added in order to be able to choose multiple
Semiconductor Group
resets the synchronizer and initiates a new frame search. The synchronous state will
be reached again, if there is only one definite framing candidate. In the case of
repeated apparent simulated candidates, the synchronizer remains in the
asynchronous state.
In asynchronous state, setting bit FMR0.FRS induces the synchronizer to lock onto
the next available framing candidate if there is one. At the same time the internal
framing pattern memory will be cleared and other possible framing candidates are
lost. (identical to the synchronization procedure implemented in FALC54 V1.1)
framing pattern candidates step by step. I.e. if in synchronous state the CRC error
counter indicates that the synchronization might have been based on an alias framing
pattern, setting of FMR0.FRS will lead to synchronization on the next candidate
available. However, only the previously assumed candidate will discarded in the
internal framing pattern memory. The latter procedure can be repeated until the
framer has locked on the right pattern (no extensive CRC errors).
The synchronizer will be completely reset and initiates a new frame search, if there is
no multiframing found. In this case bit FSR0.FSRF toggles.
General Functions and Device Architecture T1
198
PEB 2254
11.96