PEB2254H-V14 Infineon Technologies, PEB2254H-V14 Datasheet - Page 160

• Manufacturer Part Number: PEB2254H-V14
• Manufacturer: Infineon Technologies

Specifications of PEB2254H-V14

• Operating Supply Voltage (typ): 5V
• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Compliant

Pin Definitions and Function (cont’d)
Pin No. Symbol
55
69
58
Semiconductor Group
XDI
DLX
RSIGM
Input (I)
Output (O)
I
O
O
Function
Transmit Data In
Transmit data received from the system internal
highway with 4096 kbit/s or 2048 kbit/s (bit
FMR1.IMOD). Latching of data is done with
negative transitions of SCLKX.
In 4096 kbit/s mode data is sampled in the first
channel phase if RC0.SICS is low. If RC0.SICS is
high data is sampled in the second channel
phase.
The delay between the beginning of time-slot 0
and the initial edge of SCLKX (after SYPX goes
active) is determined by the values of transmit
time-slot offset XC1.XTO5 … 0, transmit
clock-slot offset XC0.XCO2 … 0 and XC1.XCOS.
Data Link Bit Transmit
This output provides a 4 kHz signal which marks
the DL-bit position within the data stream on XDI. It
can be used as transmit strobe signal for external
data link controllers. In 4096 kbit/s mode DLX is
active only during the channel phase which is
selected by RC0.SICS.
Receive Signaling Marker
– Marks the time-slots which are defined by
– When using the CAS-BR signaling scheme (bit
In 4096 kbit/s mode RSIGM is active high only
during the channel phase which is selected by
RC0.SICS.
register RTR1-4 of every received frame at
port RDO.
FMR1.SIGM = 1), the robbed bit of each
channel every six frames is marked, if it is
enabled via register XC0.BRM = 1.
160
General Features T1
PEB 2254
11.96