PEB2254H-V14 Infineon Technologies, PEB2254H-V14 Datasheet - Page 66

• Manufacturer Part Number: PEB2254H-V14
• Manufacturer: Infineon Technologies

Specifications of PEB2254H-V14

• Operating Supply Voltage (typ): 5V
• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Compliant

PEB 2254
General Functions and Device Architecture E1
2.2.3
Special Functions
Shared Flags
The closing Flag of a previously transmitted frame simultaneously becomes the opening
Flag of the following frame if there is one to be transmitted. The Shared Flag feature is
enabled by setting bit SFLG in control register CCR1.
Preamble Transmission
If enabled via register CCR3, a programmable 8-bit pattern (register PRE) is transmitted
with a selectable number of repetitions after Interframe Timefill transmission is stopped
and a new frame is ready to be sent out.
Zero Bit Insertion is disabled during preamble transmission. To guarantee correct
function the programmed preamble value should be different from Receive Address Byte
values.
Transparent Transmission and Reception
When programmed in the extended transparent mode via the MODE register
(MDS2-0 = 111), the FALC54 performs fully transparent data transmission and reception
without HDLC framing, i.e. without
• FLAG insertion and deletion
• CRC generation and checking
• Bit-stuffing
In order to enable fully transparent data transfer, bit MODE.HRAC has to be set and FF
H
has to be written to RAH2.
Data transmission is always performed out of XFIFO by directly shifting the contents of
XFIFO in the outgoing datastream. Transmission is initiated by setting CMDR.XTF
(04
). A synch-byte FF
is automatically sent before the first byte of the XFIFO will be
H
H
transmitted.
Received data is always shifted into RFIFO.
Semiconductor Group
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