PEB2254H-V14 Infineon Technologies, PEB2254H-V14 Datasheet - Page 46
PEB2254H-V14
Manufacturer Part Number
PEB2254H-V14
Description
Manufacturer
Infineon Technologies
Datasheet
1.PEB2254H-V14.pdf
(313 pages)
Specifications of PEB2254H-V14
Operating Supply Voltage (typ)
5V
Mounting
Surface Mount
Lead Free Status / RoHS Status
Compliant
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The next pages give a general description of the assigned framing formats. After
RESET, the FALC54 is switched into doubleframe format automatically.
Time-slot 0 is reserved for frame alignment word and service information. Switching
between the two applicable framing formats (doubleframe/CRC-multiframe) is done via
bit FMR2.RFS1/0 for the receiver and FMR1.XFS for the transmitter.
Line Interfacing
• Dual rail data with AMI or HDB3 coding in conjunction with double violation detection
• Single rail unipolar data (FMR0.XC1/0) with NRZ or CMI Code.
• General Alarms
• AIS: Detection is flagged by bit FRS0.AIS. Transmission is enabled via bit
• LOS: Detection is flagged by bit FRS0.LOS.
• RAI: Remote Alarm Indication is flagged by bit FRS0.RRA and RSW.RRA.
• AUXP: Detection is flagged by bit FRS1.AUXP. Transmission is enabled via bit
Channel Assignment
The channel (time-slot) assignment from the PCM line to the system internal highway is
performed without any changes of channel numbering (TS0
In receive direction, the contents of time-slot 0 are switched through transparently. In
transmit direction, contents of time-slot 0 of the outgoing PCM frame are normally
generated by the FALC54. Additionally, one transparent mode (XSP.TT0) can be
selected to achieve transparency for the complete time-slot 0. With the Transparent
Service Word Mask register (TSWM) the Si-bits, A-bit and the SA4-8 bits could be
selectively switched through transparently.
General Signaling
• S
• E bits in accordance with ITU-T G.704 and ETS 300233.
Semiconductor Group
or extended code violation detection (FMR0.EXTD). Errors can be counted by the
Code Violation Counter CVC with 16 bit length.
FMR1.XAIS.
Transmission is enabled via bit XSW.XRA.
XSP.XAP.
a
bits in accordance with ITU-T G.704 and ETS 300233.
General Functions and Device Architecture E1
46
TS0, … , TS31
PEB 2254
TS31).
11.96
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