PEB2254H-V14 Infineon Technologies, PEB2254H-V14 Datasheet - Page 157
![no-image](/images/manufacturer_photos/0/3/327/infineon_technologies_sml.jpg)
PEB2254H-V14
Manufacturer Part Number
PEB2254H-V14
Description
Manufacturer
Infineon Technologies
Datasheet
1.PEB2254H-V14.pdf
(313 pages)
Specifications of PEB2254H-V14
Operating Supply Voltage (typ)
5V
Mounting
Surface Mount
Lead Free Status / RoHS Status
Compliant
- Current page: 157 of 313
- Download datasheet (4Mb)
Pin Definitions and Function (cont’d)
Pin No. Symbol
60
72
57
Semiconductor Group
SYNC
RCLK
RDO
Input (I)
Output (O)
I
O
O
Function
Clock Synchronization
If a clock is detected at the SYNC pin the FALC54
synchronizes to this clock 1.544 MHz or
2.048 MHz (if LIM1.DCOC = 1). This pin has to be
connected to
Receive Clock
Extracted from the incoming data pulses
Clock frequency: 1544 kHz
If LIM0.ELOS is set, the RCLK is set high in case
of loss of signal (FRS0.LOS=1).
Receive Data Out
Received data which is sent to the system internal
highway with 4096 kbit/s or 2048 kbit/s (bit
FMR1.IMOD). In 4096 kbit/s mode data is shifted
out in that channel phase which is selected by
register RC0.SICS.The other channel phase is set
in tri-state. Clocking off data is done with the
falling edge of SCLKR. The delay between the
beginning of time-slot 0 and the initial edge of
SCLKR (after SYPR goes active) is determined by
the values of Receive Time-slot Offset
RC1.RTO5 … 0, Receive Clock-slot Offset
RC0.RCO2 … 0 and RC0.RCOS.
157
V
SS
if no clock is supplied.
General Features T1
PEB 2254
11.96
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