PEB2254H-V14 Infineon Technologies, PEB2254H-V14 Datasheet - Page 158

• Manufacturer Part Number: PEB2254H-V14
• Manufacturer: Infineon Technologies

Specifications of PEB2254H-V14

• Operating Supply Voltage (typ): 5V
• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Compliant

Pin Definitions and Function (cont’d)
Pin No. Symbol
71
70
68
Semiconductor Group
RFSP/
FREEZS
DLR
XMFB
Input (I)
Output (O)
O
O
O
Function
Receive Frame Synchronous Pulse/ Freeze
Signaling
If XC0.SFRZ is set to ‘0’ the Receive Frame
Synchronous Pulse (Pulse width = 648 ns) is
output on this pin. Pulse frequency: 8 kHz.
If XC0.SFRZ is set high the Freeze signaling
Status is indicated. Synchronization status signal
which informs the signaling processor that current
signaling should be frozen. It goes active if
– one or more framing bit errors are found in a
– loss of receiver synchronization, or
– a receive slip is detected.
It is cleared after an error-free superframe. During
alarm simulation, this signal goes active during
simulation steps 2 and 6.
Data Link Bit Receive
This output provides a 4 kHz signal which marks
the DL-bit position within the data stream on RDO.
It can be used as receive strobe signal for external
data link controllers. In 4096 kbit/s mode DLR is
active only during the channel phase which is
selected by RC0.SICS.
Transmit Multiframe Begin
The function depends on programming bit
XC0.MFBS:
MFBS = 1: XMFB marks the beginning of every
transmitted multiframe (XDI).
MFBS = 0: Marks the beginning of every
transmitted superframe. Additional pulses every
12 frames are provided when using ESF or F72
format.
XMFB is always active high for one 2048 kbit/s
period. In 4096 kbit/s mode XMFB is active during
the first two bits of the multiframe.
superframe,
158
General Features T1
PEB 2254
11.96