PEB2254H-V14 Infineon Technologies, PEB2254H-V14 Datasheet - Page 199

• Manufacturer Part Number: PEB2254H-V14
• Manufacturer: Infineon Technologies

Specifications of PEB2254H-V14

• Operating Supply Voltage (typ): 5V
• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Compliant

• 72-Frame Multiframe
The 72-multiframe is an alternate use of the FS-bit pattern and is used for carrying data
link information. This is done by stealing some of redundant multiframing bits after the
transmission of the 12-bit framing header (refer to table 21). The position of A and B
signaling channels (robbed bit signaling) is defined by zero-to-one and one-to-zero
transitions of the FS bits and is continued when the FS bits are replaced by the data link
bits. The use of this 24-bit data link channel, however, is not specified by the FALC54.
For access to these bits refer to section General.
Remote Alarm (Yellow Alarm) is indicated by setting bit 2 to zero in each channel. An
additional use of the D bits for alarm indication is user defined and must be done
externally.
In addition to CAS-BR, CCS and CAS-CC are also applicable to this multiframe
structure.
Synchronization Procedure
In the synchronous state terminal framing (FT bits) and multiframing (FS bits of the
framing header) are observed independently. Further reaction on framing errors
depends on the selected sync/resync procedure (via bit FMR2.SSP):
• FMR2.SSP = ‘0’: terminal frame and multiframe synchronization are combined
• FMR2.SSP = ‘1’: terminal frame and multiframe synchronization are separated
Semiconductor Group
Two errors within 4/5/6 framing bits (via bits FMR4.SSC1/0) of one of the above will
lead to the asynchronous state for terminal framing and multiframing. Additionally to
the bit FRS0.LFA, loss of multiframe alignment is reported via bit FRS0.LMFA.
The resynchronization procedure starts with synchronizing upon the terminal framing.
If the pulseframing has been regained, the search for multiframe alignment is initiated.
Multiframe synchronization has been regained after two consecutive correct
multiframe patterns have been received.
Two errors within 4/5/6 terminal framing bits will lead to the same reaction as
described above for the “combined” mode.
Two errors within 4/5/6 multiframing bits will lead to the asynchronous state only for
the multiframing. Loss of multiframe alignment is reported via bit FRS0.LMFA. The
state of terminal framing is not influenced.
Now, the resynchronization procedure includes only the search for multiframe
alignment. Multiframe synchronization has been regained after two consecutive
correct multiframe patterns have been received.
General Functions and Device Architecture T1
199
PEB 2254
11.96