PEB2254H-V14 Infineon Technologies, PEB2254H-V14 Datasheet - Page 252

• Manufacturer Part Number: PEB2254H-V14
• Manufacturer: Infineon Technologies

Specifications of PEB2254H-V14

• Operating Supply Voltage (typ): 5V
• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Compliant

SICS…
CRCI…
XCRCI…
RDIS…
RCO2…RCO0… Receive Clock-Slot Offset
Receive Control 1 (Read/Write)
Value after RESET: 00
RC1
RRAM…
Semiconductor Group
7
System Interface Channel Select
Only applicable if bit FMR1.IMOD (4 MHz system interface) is set.
Automatic CRC6 Bit Inversion
If set, all CRC bits of one outgoing extended multiframe are inverted
in case a CRC error is flagged for the previous received multiframe.
This function is logically ORed with RC0.XCRCI.
Transmit CRC6 Bit Inversion
If set, the CRC bits in the outgoing data stream are inverted before
transmission. This function is logically ORed with RC0.CRCI.
Receive Data Input Sense
0
1
Initial value loaded into the receive bit counter at the trigger edge of
SCLKR when the synchronous pulse at port SYPR is active (see
figure 56).
Receive Remote Alarm Mode
The conditions for remote (yellow) alarm (FRS0.RRA) detection can
be selected via this bit to allow detection even in the presence of
BER 10**-3:
RRAM = 0
Detection
0
1
RRAM
H
Received data is output on port RDO in the first channel phase.
Data in the second channel phase is tri-stated.
Data on pin XDI is sampled only in the first channel phase. Data
in the second channel phase is ignored.
Data on port RDO is output in the second channel phase. The
first channel phase is tri-stated. Sampling of data from the
system highway is done in the second channel phase.
Inputs: RDIP, RDIN active low, input ROID is active high
Inputs: RDIP, RDIN active high, input ROID is active low
RTO5
252
Operational Description T1
0
RTO0
PEB 2254
(23)
11.96