PEB2254H-V14 Infineon Technologies, PEB2254H-V14 Datasheet - Page 67

• Manufacturer Part Number: PEB2254H-V14
• Manufacturer: Infineon Technologies

Specifications of PEB2254H-V14

• Operating Supply Voltage (typ): 5V
• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Compliant

PEB 2254
General Functions and Device Architecture E1
Cyclic Transmission (fully transparent)
If the extended transparent mode is selected, the FALC54 supports the continuous
transmission of the contents of the transmit FIFO.
After having written 1 to 32 bytes to XFIFO, the command XREP.XTF via the CMDR
register (bit 7
0 = ‘00100100’ = 24
) forces the FALC54 to repeatedly transmit the
H
data stored in XFIFO to the remote end.
The cyclic transmission continues until a reset command (CMDR. SRES) is issued or
with resetting CMDR.XREP, after which continuous ‘1’-s are transmitted.
Note: During cyclic transmission the XREP-bit has to be set with every write operation
to CMDR.
CRC ON/OFF Features
As an option in HDLC mode the internal handling of received and transmitted CRC
checksum can be influenced via control bits CCR3.RCRC and CCR3.XCRC.
Receive Direction
The received CRC checksum is always assumed to be in the 2 (CRC-ITU) last bytes of
a frame, immediately preceding a closing flag. If CCR3.RCRC is set, the received CRC
checksum will be written to RFIFO where it precedes the frame status byte (contents of
register RSIS). The received CRC checksum is additionally checked for correctness. If
HDLC mode is selected, the limits for ‘Valid Frame’ check are modified (refer to
description of bit RSIS.VFR).
Transmit Direction
If CCR3.XCRC is set, the CRC checksum is not generated internally. The checksum has
to be provided via the transmit FIFO (XFIFO) as the last two bytes. The transmitted frame
will only be closed automatically with a (closing) flag.
The FALC54 does not check whether the length of the frame, i.e. the number of bytes to
be transmitted makes sense or not.
Receive Address Pushed to RFIFO
The address field of received frames can be pushed to RFIFO (first one/two bytes of the
frame). This function is especially useful in conjunction with the extended address
recognition. It is enabled by setting control bit CCR3.RADD.
Semiconductor Group
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