PEB2254H-V14 Infineon Technologies, PEB2254H-V14 Datasheet - Page 259

• Manufacturer Part Number: PEB2254H-V14
• Manufacturer: Infineon Technologies

Specifications of PEB2254H-V14

• Operating Supply Voltage (typ): 5V
• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Compliant

RIL2…RIL0…
DCOC
JATT…RL...
DRS…
Semiconductor Group
1 =
Receive Input Threshold
Only valid if analog line interface is selected (LIM1.DRS=0).
No signal will be declared if the voltage between pins RL1 and RL2
drops below the limits programmed via bits RIL2-0 and the received
data stream has no transition for a period defined in the PCD register.
The threshold where no signal will be declared is programmable via
the RIL2-0 bits.
000 = 1.36 V
001 = 1.04 V
010 = 0.84 V
011 = 0.62 V
100 = 0.43 V
101 = 0.32 V
110 = 0.22 V
111 = Not assigned
DCO1 Control
A one in this bit position will enable to synchronize the internal
generated systems clocks from DCO1 to an external 2 MHz clock
provided on pin SYNC.
Transmit Jitter Attenuator / Remote Loop
00 = Normal operation. The transmit jitter attenuator is disabled.
01 = Remote Loop active without transmit jitter attenuator enabled.
10 = not assigned
11 = Remote Loop and jitter attenuator active. Received data from
0 =
1 =
Dual Rail Select
Pin XCLK provides a 8 KHz frame synchronization pulse which
is active high for one 2 MHz cycle (pulse width = 488 ns).
Transmit data will bypass the buffer.
Transmit data will bypass the buffer.
pins RL1/2 or RDIP/N or ROID will be sent jitter free on ports
XL1/2 or XDOP/N or XOID.
The ternary interface is selected. Multifunction ports RL1/2 and
XL1/2 become analog in/outputs.
The digital dual rail interface is selected. Received data is
latched on multifunction ports RDIP/RDIN while transmit data is
output on pins XDOP/XDON.
259
Operational Description T1
PEB 2254
11.96