PEB2254H-V14 Infineon Technologies, PEB2254H-V14 Datasheet - Page 41

• Manufacturer Part Number: PEB2254H-V14
• Manufacturer: Infineon Technologies

Specifications of PEB2254H-V14

• Operating Supply Voltage (typ): 5V
• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Compliant

PEB 2254
General Functions and Device Architecture E1
Latching of data is controlled by the System Clock (SCLKX) and the Synchronous Pulse
(SYPX) in conjunction with the programmed offset values for the Transmit
Time-slot/Clock-slot Counters.
The clock for the transmit data is internal derived directly from the system clock
(SCLKX). Consequently, the data received from the system interface is switched
through.
Transmit Signaling Controller
Similar to the receive signaling controller the same signaling methods and the same
time-slot assignment are provided. The signaling information has to be written in the
Transmit FIFO (XFIFO). With a Transmit Frame command the signaling information will
be sent in the corresponding time-slots. The signaling will be internally multiplexed with
the data at port XDI.
If the extended transparent mode is selected, the FALC54 supports the continuous
transmission of the contents of the XFIFO. The cyclic transmission continuous until the
Transmitter Reset command (CMDR.SRES) is issued or CMDR.XREP is reset.
In case of channel associated signaling the complete CAS multiframe have to be written
to the XS1-16 registers. The contents of these registers will be sent in TS16.
In case of CCS the signaling procedure HDLC/SDLC is supported with generation of
Preambles and FLAGs, CRC generation and bit-stuffing.
In transmit direction the FALC54 offers the flexibility to insert data during certain
time-slots which are defined via registers TTR1-4 or to insert the S
bits enabled via
a
XC0.SA8E-4E. Any combination of time-slots bits can be programmed independent for
the receive and transmit direction.
If the FALC54 is optioned for no signaling, the channels in the data stream from the
system interface will pass the FALC54 undisturbed.
Transmitter
The serial bit stream is then processed by the transmitter which has the following
functions:
• Frame/multiframe synthesis of one of the two selectable framing formats
• Insertion of service and data link information
• AIS generation (Alarm indication signal)
• Remote alarm generation
• Auxiliary pattern generation
• CRC generation and insertion of CRC bits
CRC bits inversion in case of a previously received CRC error
The multiframe boundries of the transmitter may be externally synchronized by using the
XMFS pin. This feature is required if signaling- and service- bits are routed through the
switching network and are inserted in transmit direction via the system interface.
Semiconductor Group
41
11.96