PEB2254H-V14 Infineon Technologies, PEB2254H-V14 Datasheet - Page 188

• Manufacturer Part Number: PEB2254H-V14
• Manufacturer: Infineon Technologies

Specifications of PEB2254H-V14

• Operating Supply Voltage (typ): 5V
• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Compliant

PEB 2254
General Functions and Device Architecture T1
ISR0.PDEN. Generation of the interrupt status can be programmed either with the
detection or with any change of state of the pulse density alarm (IPC.SCI).
System Clocks and System Pulses for Transmitter and Receiver
The FALC54 offers a flexible feature for system designers where different system clocks
and system pulses are necessary. The interface to the receive system highway will be
clocked via pin SCLKR, while the interface to the transmit system highway is clocked via
pin SCLKX. The frequency on pin SCLKR/X must fixed 8.192 MHz.
The signals on pin SYPR in conjunction with the assigned timeslot offset in register RC0
and RC1 will define the beginning of a frame on the receive system highway. The signal
on pin SYPX in conjunction with the assigned timeslot offset in register XC0 and XC1 will
define the beginning of a frame on the transmit system highway.
Error Performance Monitoring
The FALC54 supports the error performance monitoring by detecting following alarms in
the received data.
• Framing errors
• CRC errors
• Code violations
• Loss of frame alignment
• Loss of signal
• Alarm indication signal
• Slip
With a programmable interrupt mask (register IMR4) all these error events could
generate an Errored Second interrupt (ES) if enabled. Additionally a one Second
interrupt could be generated to indicate that the ES interrupt has to be read. If the ES
interrupt is set the enabled alarm status bits or the error counters have to be examined.
Additionally an 16 bit wide Errored Block Counter is realized. In ESF format this counter
will be incremented once per multiframe if a multiframe has been received with a CRC
error or an errored frame alignment has been detected.
Automatic Remote Alarm (Yellow Alarm) Access
If the receiver has lost its synchronization a remote alarm (yellow alarm) could be sent if
enabled via bit FMR2.AXRA to the distant end. The remote alarm will be automatically
generated in the outgoing data stream if the receiver is in asynchronous state
(FRS0.LFA bit is set). In synchronous state the remote alarm bit will be removed.
Semiconductor Group
188
11.96