PEB2254H-V14 Infineon Technologies, PEB2254H-V14 Datasheet - Page 51

• Manufacturer Part Number: PEB2254H-V14
• Manufacturer: Infineon Technologies

Specifications of PEB2254H-V14

• Operating Supply Voltage (typ): 5V
• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Compliant

For transmit direction, contents of time-slot 0 are additionally determined by the selected
transparent mode:
Mode
–
XSP.TT0
TSWM.TSIF
TSWM.TSIS
TSWM.TRA
TSWM.TSA4–8
1)
2)
3)
The CRC procedure is automatically invoked when the multiframe structure is enabled.
CRC errors in the received data stream are counted by the 16 bit CRC Error Counter
CEC (one error per submultiframe, maximum).
Additionally a CRC4 error interrupt status ISR0.CRC4 can be generated if enabled via
IMR0.CRC4.
All CRC bits of one outgoing submultiframe are automatically inverted in case a CRC
error is flagged for the previous received submultiframe. This function is enabled via bit
RC0.CRCI. Setting the bit RC0.XCRCI will invert the CRC bits before transmission to the
distant end. The function of RC0.XCRCI and RC0.CRCI are logically ored.
Synchronization Procedure
Multiframe alignment is assumed to have been lost if doubleframe alignment has been
lost (flagged at status bits FRS0.LFA and FRS0.LMFA). The rising edge of these bits will
cause an interrupt status bits ISR2.LFA + ISR2.LMFA.
The multiframe resynchronization procedure starts when Doubleframe alignment has
been regained which is indicated by an interrupt status bit ISR2.FAR. For Doubleframe
synchronization refer to section Doubleframe Format. It may also be invoked by the user
by setting
– bit FMR0.FRS for complete Doubleframe and multiframe re-synchronization
– bit FMR1.MFCS for multiframe re-synchronization only.
The CRC checking mechanism will be enabled after the first correct multiframe pattern
has been found. However, CRC errors will not be counted in asynchronous state.
Semiconductor Group
The S
Additionally, automatic transmission of submultiframe error indication is selectable
Automatic transmission of the A-bit is selectable
a
-bit register XSA4-8 may be used optionally
Framing + CRC A Bit
(int. generated)
via pin XDI
(int. generated)
(int. generated)
(int. generated)
(int. generated)
Transparent Source for
XSW.XRA
via pin XDI
XSW.XRA
XSW.XRA
via pin XDI
XSW.XRA
General Functions and Device Architecture E1
51
1)
1)
1)
1)
Sa Bits
XSW.XY0 … 4
via pin XDI
XSW.XY0 … 4
XSW.XY0 … 4
XSW.XY0 … 4
via pin XDI
2)
2)
2)
2)
E Bits
XSP.XS13/XS15
via pin XDI
(int. generated)
via pin XDI
XSP.XS13/XS15
XSP.XS13/XS15
PEB 2254
11.96
3)
3)
3)