PEB2254H-V14 Infineon Technologies, PEB2254H-V14 Datasheet - Page 32

• Manufacturer Part Number: PEB2254H-V14
• Manufacturer: Infineon Technologies

Specifications of PEB2254H-V14

• Operating Supply Voltage (typ): 5V
• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Compliant

PEB 2254
General Functions and Device Architecture E1
Receive Clock and Data Recovery
The analog received signal at port RL1/2 is equalized and then peak-detected to
produce a digital signal. The digital received signal at port RDIP/N is directly forwarded
to the DPLL. The receive clock and data recovery extracts the route clock RCLK from the
data stream received at the RL1/2, RDIP/RDIN or ROID lines and converts the data
stream into a single rail, unipolar bit stream. The clock and data recovery works with the
frequency supplied by XTAL1 and XTAL2. Normally the clock that is output via pin RCLK
is the recovered clock from the signal provided by RL1/2 or RDIP/N has a duty cycle
close to 50 %. The free run frequency is defined by XTAL1/2 devided by 8 in periods with
no signal.
Receive Line Coding
The HDB3 line code or the AMI coding is provided for the data received from the ternary
or the dual rail interface. In case of the optical interface a selection between the NRZ
code and the CMI Code (1T2B) with HDB3 postprocessing is provided. If CMI code
(1T2B) is selected the receive route clock will be recovered from the data stream. The
1T2B decoder does not correct any errors. In case of NRZ coding data will be latched
with the falling edge of pin RCLKI. The HDB3 code is used along with double violation
detection or extended code violation detection (selectable). In AMI code all code
violations will be detected.
The detected errors increment the code violation counter (16 bits length).
When using the optical interface with NRZ coding, the decoder is by-passed and no code
violations will be detected.
Additionally, the receive line interface comprises the alarm detection for Alarm Indication
Signal AIS, the Loss of Signal LOS and the Auxiliary Pattern AUXP (unframed and
continuous bitstream of alternating ONEs and ZEROs).
The signal at the ternary interface is received at both ends of a transformer.
The operating modes 75 or 120
are selectable by switching resistors in parallel. This
selection does not require changing transformers.
Figure 10
Receiver Configuration
Semiconductor Group
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