PEB2254H-V14 Infineon Technologies, PEB2254H-V14 Datasheet - Page 150

• Manufacturer Part Number: PEB2254H-V14
• Manufacturer: Infineon Technologies

Specifications of PEB2254H-V14

• Operating Supply Voltage (typ): 5V
• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Compliant

Pin Definitions and Function (cont’d)
Pin No. Symbol
50
51
52
54
Semiconductor Group
RD/DS
WR/RW
CS
RES
Input (I)
Output (O)
I
I
I
I
Function
Read Enable (Siemens/Intel bus mode)
This signal indicates a read operation. When the
FALC54 is selected via CS the RD signal enables
the bus drivers to output data from an internal
register addressed via A0 … A6 on to Data Bus.
For more information about control/status register
and FIFO access in the different bus interface
modes refer to chapter 4.6.
Data Strobe (Motorola bus mode)
This pin serves as input to control read/write
operations.
Write Enable (Siemens/Intel bus mode)
This signal indicates a write operation. When CS
is active the FALC54 loads an internal register
with data provided via the Data Bus. For more
information about control/status register and FIFO
access in the different bus interface modes refer
to chapter 4.6.
Read/Write Enable (Motorola bus mode)
This signal distinguishes between read and write
operation.
Chip Select
A low signal selects the FALC54 for read/write
operations.
Reset
A high signal on this pin forces the FALC54 into
reset state. During Reset the FALC54 needs active
clocks on pins SCLKR, SCLKX, XTAL1 and
XTAL3.
During Reset
– all uni-directional output stages are in high-
– all bi-directional output stages (data bus) are in
impedance state, except pins CLK16M,
CLK12M, CLK8M, CLKX, FSC, XCLK and
RCLK
high-impedance state if signal RD is “high”,
“output” XTAL2/4 is in high-impedance if input
XTAL1/3 is “high”.
150
General Features T1
PEB 2254
11.96