PEB2254H-V14 Infineon Technologies, PEB2254H-V14 Datasheet - Page 77

• Manufacturer Part Number: PEB2254H-V14
• Manufacturer: Infineon Technologies

Specifications of PEB2254H-V14

• Operating Supply Voltage (typ): 5V
• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Compliant

PEB 2254
Operational Description E1
HDLC Data Transmission
In transmit direction 2x32 byte FIFO buffers are provided. After checking the XFIFO
status by polling the bit SIS.XFW or after an interrupt ISR1.XPR (Transmit Pool Ready),
up to 32 bytes may be entered by the CPU to the XFIFO.
The transmission of a frame can be started by issuing a XTF or XHF command via the
command register. If enabled, a specified number of preambles (register PRE) are
optionally sent out before transmission of the current frame starts. If the transmit
command does not include an end of message indication (CMDR.XME), the FALC54 will
repeatedly request for the next data block by means of a XPR interrupt as soon as no
more than 32 bytes are stored in the XFIFO, i.e. a 32-byte pool is accessible to the CPU.
This process will be repeated until the CPU indicates the end of message per XME
command, after which frame transmission is finished correctly by appending the CRC
and closing flag sequence. Consecutive frames may be share a flag (enabled via
CCR1.SFLG), or may be transmitted as back-to-back frames, if service of XFIFO is quick
enough.
In case no more data is available in the XFIFO prior to the arrival of XME, the
transmission of the frame is terminated with an abort sequence and the CPU is notified
per interrupt ISR1.XDU. The frame may be aborted per software CMDR.SRES.
The data transmission sequence, from the CPU’s point of view, is outlined in figure 30.
Semiconductor Group
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