PEB2254H-V14 Infineon Technologies, PEB2254H-V14 Datasheet - Page 258

• Manufacturer Part Number: PEB2254H-V14
• Manufacturer: Infineon Technologies

Specifications of PEB2254H-V14

• Operating Supply Voltage (typ): 5V
• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Compliant

EQON…
ELOS
LL…
MAS…
Line Interface Mode 1 (Read/Write)
Value after RESET: 00
LIM1
EFSC…
Semiconductor Group
7
EFSC
Receive Equalizer On
0
1
Enable Loss of Signal
0...
1...
Local Loop
0
Master Mode
0
Enable Frame Synchronization Pulse
0 =
1
1
RIL2
H
Normal operation. The extracted receive clock is output via pin
In case of loss of signal (FRS0.LOS=1) the RCLK is set high. If
6 dB Receiver
18 dB Equalizer on
RCLK.
FRS0.LOS=0 the received clock is output via RCLK.
Normal operation
Local loop active. The local loopback mode disconnects the
receive lines RL1/RL2 resp. RDIP/RDIN from the receiver.
Instead of the signals coming from the line the data provided by
system interface are routed through the analog receiver back to
the system interface. The unipolar bit stream will be
undisturbed transmitted on the line. Receiver and transmitter
coding must be identical.
Slave mode
Master mode on. If this bit is set and the SYNC pin is connected
to
internal DCO’s of the jitter attenuator are centered and the
system clocks which are output via CLK8M/CLKX are stable
(divided from the DCO frequencies). If a clock (1.544 MHz or
2.048 MHz) is detected at the SYNC pin the FALC54
synchronizes automatically to this clock. The production
tolerance is approximately
C
The transmit clock is output via pin XCLK.
Load
V
RIL1
SS
= 15 pF.
the FALC54 works as a master for the system. The
RIL0
258
DCOC
30 ppm of the crystal frequency if
JATT
Operational Description T1
RL
0
DRS
PEB 2254
(35)
11.96