PEB2254H-V14 Infineon Technologies, PEB2254H-V14 Datasheet - Page 234

• Manufacturer Part Number: PEB2254H-V14
• Manufacturer: Infineon Technologies

Specifications of PEB2254H-V14

• Operating Supply Voltage (typ): 5V
• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Compliant

XME…
SRES…
Mode Register (Read/Write)
Value after RESET: 00
MDS2-0…
Semiconductor Group
MODE
7
MDS2
Transmit Message End
Indicates that the data block written last to the transmit FIFO
completes the current frame. The FALC54 can terminate the
transmission operation properly by appending the CRC and the
closing flag sequence to the data.
Signaling Transmitter Reset
The transmitter of the signaling controller will be reset. XFIFO is
cleared of any data and an abort sequence (seven 1’s) followed by
interframe time fill is transmitted. In response to XRES an XPR
interrupt is generated.
This command can be used by the CPU to abort a frame currently in
transmission.
Note: The maximum time between writing to the CMDR register and
Mode Select
The operating mode of the HDLC controller is selected.
000
001
010
011
100
101
110
111
MDS1
H
the execution of the command depends on FMR1.IMOD. If
FMR1.IMOD is set it takes 10 SCLKX cycles and 5 SCLKX
cycles if FMR1.IMOD is cleared. Therefore, if the CPU
operates with a very high clock rate in comparison with the
FALC's clock, it is recommended that bit SIS.CEC should be
checked before writing to the CMDR register to avoid any loss
of commands.
Reserved
Reserved
1 byte address comparison mode (RAL1, 2)
2 byte address comparison mode (RAH1, 2 and RAL1, 2)
No address comparison
1 byte address comparison mode (RAH1, 2)
Reserved
No HDLC framing mode 1
MDS0
BRAC
234
HRAC
Operational Description T1
0
PEB 2254
(03)
11.96