PEB2254H-V14 Infineon Technologies, PEB2254H-V14 Datasheet - Page 56

• Manufacturer Part Number: PEB2254H-V14
• Manufacturer: Infineon Technologies

Specifications of PEB2254H-V14

• Operating Supply Voltage (typ): 5V
• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Compliant

E-Bit Access
Due to signaling requirements, the E bits of frame 13 and frame 15 of the CRC
multiframe can be used to indicate received errored submultiframes:
Submultiframe I status
Submultiframe II status
no CRC error:
CRC error:
Standard Procedure
After reading the Submultiframe Error Indication RSP.SI1 and RSP.SI2, the
microprocessor has to update contents of register XSP (XS13, XS15). Access to these
registers has to be synchronized to Transmit or Receive Multiframe Begin Interrupts
(ISR0.RMB or ISR1.XMB).
In the double- and multiframe asynchronous state the E-bits are set to zero. However
they can be set to one in the async. state if enabled via bit XSP.EBP. In the multiframe
sync. state the E-bits are processed according to ITU-T G.704 independent of bit
XSP.EBP.
Automatic Mode
By setting bit XSP.AXS status information of received submultiframes is automatically
inserted in E-bit position of the outgoing CRC Multiframe without any further
interventions of the microprocessor.
Submultiframe Error Indication Counter
The EBC (E-Bit) Counter EBCL and EBCH (16 bits) counts zeros in E-bit position of
frame 13 and 15 of every received CRC Multiframe. This counter option gives
information about the outgoing transmit PCM line if the E bits are used by the remote end
for submultiframe error indication. Incrementing is only possible in the multiframe
synchronous state.
Note: E-bits may be processed via the system interface. Setting bit TSWM.TSIS enables
Semiconductor Group
transparency for E bits in transmit direction (refer to table 6).
:
:
E- Bit located in frame 13
E- Bit located in frame 15
E = 1
E = 0
General Functions and Device Architecture E1
56
PEB 2254
11.96