PEB2254H-V14 Infineon Technologies, PEB2254H-V14 Datasheet - Page 274

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PEB2254H-V14

Manufacturer Part Number
PEB2254H-V14
Description
Manufacturer
Infineon Technologies
Datasheet

Specifications of PEB2254H-V14

Operating Supply Voltage (typ)
5V
Mounting
Surface Mount
Lead Free Status / RoHS Status
Compliant
CRC Error Counter (READ)
CECL
CECH
CR15…CR0…
Semiconductor Group
7
7
CR15
CR7
CRC Errors
No function if CRC6 procedure or ESF format are disabled.
In ESF mode, the 16-bit counter will be incremented when a
multiframe has been received with a CRC error. CRC errors will not
be counted during asynchronous state.
Clearing and updating the counter is done according to bit
FMR1.ECM.
During alarm simulation, the counter is incremented once per
multiframe.
If this bit is reset the error counter is permanently updated in the
buffer. For correct read access of the error counter bit DEC.DCEC
has to be set. With the rising edge of this bit updating the buffer will
be stopped and the error counter will be reset. Bit DEC.DCEC will
automatically be reset with reading the error counter high byte.
If FMR1.ECM is set every second (interrupt ISR3.SEC) the error
counter will be latched and then automatically reset. The latched error
counter state should be read within the next second.
274
Operational Description T1
0
0
CR0
CR8
PEB 2254
(54)
(55)
11.96

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