PEB2254H-V14 Infineon Technologies, PEB2254H-V14 Datasheet - Page 146
![no-image](/images/manufacturer_photos/0/3/327/infineon_technologies_sml.jpg)
PEB2254H-V14
Manufacturer Part Number
PEB2254H-V14
Description
Manufacturer
Infineon Technologies
Datasheet
1.PEB2254H-V14.pdf
(313 pages)
Specifications of PEB2254H-V14
Operating Supply Voltage (typ)
5V
Mounting
Surface Mount
Lead Free Status / RoHS Status
Compliant
- Current page: 146 of 313
- Download datasheet (4Mb)
Frame Aligner
• Frame alignment/synthesis for 1544 kbit/s according to ITU-T G.704
• Meets newest ITU-T Rec's, ANSI T1 and AT&T Technical References
• Programmable formats for
• Selectable conditions for loss of frame alignment
• Error checking via CRC6 procedures according to ITU-T G. 706
• Performance monitoring
• Insertion and extraction of alarms (AIS, Remote (Yellow) Alarm, …)
• IDLE code insertion for selectable channels
• 8192 kHz System clock frequency different for receiver and transmitter
• Selectable 2048/4096 kbit/s backplane interface with programmable receive/transmit
• Two-frame elastic store for receive route clock wander and jitter compensation;
• One frame elastic store for transmit route clock wander and jitter compensation
• Support for different data link schemes
• Clear channel capabilities
• Flexible transparent modes
• In band Loop Code detection and generation according to TR 62411
• Channel loop back, line loop back or Payload loop back capabilities (AT&T TR 54016)
Signaling Controller
• HDLC controller
• DL-channel protocol for ESF format according to T1.403-1989 ANSI specification or
• Robbed bit signaling with last look capability
• DL-access for F72 (SLC96) format
• Transparent Mode
• FIFO buffers (64 bytes deep) for efficient transfer of data packets.
• Time-slot assignment
Semiconductor Group
PCM 24: 4-Frame Multiframe (F4), 12-Frame Multiframe (F12, D3/4), Extended
Superframe (ESF), Remote Switch Mode (F72, SLC96)
16 bit counter for CRC-, framing errors, code violations, Errored blocks
shifts
Programmable tri-state function of 4096 kbit/s output via RDO
controlled slip capability and slip indication
Bit stuffing, CRC check and generation, flag generation, flag and address recognition,
handling of bit oriented functions, programmable preamble
according to AT&T TR54016.
Any combination of time slots selectable for data transfer independent of signaling
mode. Useful for Fractional T1 applications.
146
General Features T1
PEB 2254
11.96
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