PEB2254H-V14 Infineon Technologies, PEB2254H-V14 Datasheet - Page 40

• Manufacturer Part Number: PEB2254H-V14
• Manufacturer: Infineon Technologies

Specifications of PEB2254H-V14

• Operating Supply Voltage (typ): 5V
• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Compliant

PEB 2254
General Functions and Device Architecture E1
Receive Signaling Controller
The receive signaling controller can be programmed to operate in various signaling
modes. The FALC54 will perform the following signaling and data link methods:
• Message Oriented Signaling also called Common Channel Signaling CCS
• Channel Associated Signaling CAS
The signaling information is carried in time-slot 16 (TS16).
The signaling controller samples the bit stream which is output on pin RDO.
In case of channel associated signaling data is sampled on the receive line side clocked
with the extracted receive route clock and stored in registers RS1-16. The signaling
procedure will be done as it is described in ITU-T G.704 and G.732.
The main functions are:
• Synchronization to a CAS multiframe
• Detection of AIS and Remote Alarm in CAS multiframes
• Separation of CAS Service bits X1-X3
• Storing of received signaling data in registers RS1-16.
Updating of the received signaling information is inhibited if the TS0 or TS16 multiframe
alignment is lost.
In case of common channel signaling the signaling procedure HDLC/SDLC will be
supported. The received data flow and the address recognition features can be
performed in very flexible way, to satisfy almost any practical requirements. Depending
on the selected address mode, the FALC54 can perform a 1 or 2 byte address
recognition. All frames with valid addresses are forwarded directly via the Receive FIFO
(RFIFO) to the system memory. The HDLC control-field, data in the I-field and an
additional status byte are temporarily stored in the RFIFO. The HDLC control-field and
additional information can also be read from special registers.
In extended transparent mode, fully transparent data reception without HDLC framing is
performed, i.e. without FLAG recognition, CRC checking or bit-stuffing. This allows the
user specific protocol variations. The received data are stored in the RFIFO.
The FALC54 offers the flexibility to extract data during certain time-slots which are
defined via registers RTR1-4 or to extract the S
bits enabled via XC0.SA8E-4E. Any
a
combination of time-slots or S
bits can be programmed.
a
2.1.2
Transmit Path
The inverse functions are performed for the transmit direction.
The PCM data is received from the system internal highway at port XDI with 2048 kbit/s
or 4096 kbit/s. The channel assignment is equivalent to the receive direction.
The contents of selectable channels (time-slots) can be overwritten by the pattern
defined via register IDLE. The selection of “idle channels” is done by programming the
four-byte registers ICB1 … ICB4.
Semiconductor Group
40
11.96