PEB2254H-V14 Infineon Technologies, PEB2254H-V14 Datasheet - Page 237

• Manufacturer Part Number: PEB2254H-V14
• Manufacturer: Infineon Technologies

Specifications of PEB2254H-V14

• Operating Supply Voltage (typ): 5V
• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Compliant

IC0, IC1…
Common Configuration Register 1 (READ/WRITE)
Value after RESET: 00
CCR1
SFLG…
BRM…
EDLX…
EITS…
ITF…
Semiconductor Group
7
SFLG
Interrupt Port Configuration
These bits define the function of the interrupt output stage (pin INT):
IOC1
X
0
1
Enable Shared Flags
If this bit is set, the closing FLAG of a preceding frame simultaneously
becomes the opening FLAG of the following frame.
BOM Receive Mode (significant in BOM mode only)
0
1
Enable DL Bit Access via the Transmit FIFO
A one in this bit position enables the internal DL- bit access via the
transmit FIFO of the signaling controller. FMR1.EDL has to be
cleared to enable the sending of the contents of the XFIFO on the
ports XL1/2 or XDOP/N.
Enable Internal Time-Slot 0-31 Signaling
0…
1…
Interframe Time Fill
Determines the idle (= no data to send) state of the transmit data
coming from the signaling controller.
0
1
BRM
H
Internal signaling in time-slots 0-31 defined via registers
Internal signaling in time-slots 0-31 defined via registers
RTR1-4 or TTR1-4 is disabled.
RTR1-4 or TTR1-4 is enabled.
10 byte packets
Continuous reception
Continuous logical ‘1’ is output
Continuous FLAG sequences are output (‘01111110’ bit
patterns)
EDLX
IOC0
0
1
1
EITS
Function
Open drain output
Push/pull output, active low
Push/pull output, active high
237
ITF
Operational Description T1
RFT1
0
RFT0
PEB 2254
(09)
11.96