PEB2254H-V14 Infineon Technologies, PEB2254H-V14 Datasheet - Page 121

• Manufacturer Part Number: PEB2254H-V14
• Manufacturer: Infineon Technologies

Specifications of PEB2254H-V14

• Operating Supply Voltage (typ): 5V
• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Compliant

RRA…
AUXP…
Semiconductor Group
The following conditions have to be detected to regain synchronous
state:
– The presence of the correct FAS word in frame n.
– The presence of the correct service word (bit 2 = 1) in frame n + 1.
– For a second time the presence of a correct FAS word in frame
The bit is cleared when synchronization has been regained (directly
after the second correct FAS word of the procedure described above
has been received).
If the CRC-multiframe structure is enabled by setting bit FMR2.RFS1,
multiframe alignment is assumed to be lost if pulse-frame
synchronization has been lost. The resynchronization procedure for
multiframe alignment starts after the bit FRS0.LFA has been cleared.
Multiframe alignment has been regained if two consecutive CRC-
multiframes have been received without a framing error (refer to
FRS0.LMFA).
The bit will be set during alarm simulation and reset if FMR0.SIM is
cleared and no alarm condition exists.
If bit FRS0.LFA is cleared a loss of frame alignment recovery interrupt
status ISR2.FAR will be generated.
Receive Remote Alarm
Set if bit 3 of the received service word is set. An alarm interrupt
status ISR2.RA can be generated if the alarm condition is detected.
FRS0.RRA will be cleared when no alarm is detected. At the same
time a remote alarm recovery interrupt status ISR2.RAR will be
generated.
The bit RSW.RRA has the same function.
Both status and interrupt status bits will be set during alarm
simulation.
Auxiliary Pattern Indication
This bit is set when 254 or more ‘10’ are received in a time interval of
250 s and the frame alignment is lost FRS0.LFA = 1. An interrupt
status ISR3.API will be generated if this bit is set.
The bit will be reset when no auxiliary pattern condition is detected.
The bit will also be set during alarm simulation and reset if FMR0.SIM
is cleared and no alarm condition exists.
n + 2.
121
Operational Description E1
PEB 2254
11.96