PEB2254H-V14 Infineon Technologies, PEB2254H-V14 Datasheet - Page 272

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PEB2254H-V14

Manufacturer Part Number
PEB2254H-V14
Description
Manufacturer
Infineon Technologies
Datasheet

Specifications of PEB2254H-V14

Operating Supply Voltage (typ)
5V
Mounting
Surface Mount
Lead Free Status / RoHS Status
Compliant
Framing Error Counter (READ)
FECL
FECH
FE15…FE0…
Semiconductor Group
7
7
FE15
FE7
Framing Errors
This 16-bit counter will be incremented when incorrect FT and FS bits
in F4, F12 and F72 format or incorrect FAS bits in ESF format are
received.
Framing errors will not be counted during asynchronous state.
Clearing and updating the counter is done according to bit
FMR1.ECM.
During alarm simulation, the counter will be incremented twice.
If this bit is reset the error counter is permanently updated in the
buffer. For correct read access of the error counter bit DEC.DFEC
has to be set. With the rising edge of this bit updating the buffer will
be stopped and the error counter will be reset. Bit DEC.DFEC will
automatically be reset with reading the error counter high byte.
If FMR1.ECM is set every second (interrupt ISR3.SEC) the error
counter will be latched and then automatically reset. The latched error
counter state should be read within the next second.
272
Operational Description T1
0
0
FE0
FE8
PEB 2254
(50)
(51)
11.96

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