PEB2254H-V14 Infineon Technologies, PEB2254H-V14 Datasheet - Page 130

• Manufacturer Part Number: PEB2254H-V14
• Manufacturer: Infineon Technologies

Specifications of PEB2254H-V14

• Operating Supply Voltage (typ): 5V
• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Compliant

CRC Error Counter 3 (Read)
CEC3L
CEC3H
CE15…CE0…
Semiconductor Group
7
7
CE15
CE7
CRC Error Counter (detected at T Ref. Point via Sa6 -Bit)
If doubleframe format is selected, CEC3H/L has no function. If CRC-
multiframe mode is enabled, CEC3H/L works as SA6 Bit error
indication counter (16 bits) which counts the SA6 Bit sequence 0010
and 0011in every received CRC submultiframe.
Incrementing the counter is only possible in the multiframe
synchronous state FRS0.LMFA = 0.
SA6 Bit sequence: SA61, SA62, SA63, SA64 = 0010 or 0011 where
SA61 is received in frame 1 or 9 in every multiframe.
Clearing and updating the counter is done according to bit
FMR1.ECM.
During alarm simulation, the counter is incremented once per
multiframe up to its saturation.
If this bit is reset the error counter is permanently updated in the
buffer. For correct read access of the error counter bit DEC.DCEC3
has to be set. With the rising edge of this bit updating the buffer will
be stopped and the error counter will be reset. Bit DEC.DCEC3 will
automatically be reset with reading the error counter high byte.
If FMR1.ECM is set every second (interrupt ISR3.SEC) the error
counter will be latched and then automatically reset. The latched error
counter state should be read within the next second.
130
Operational Description E1
0
0
CE0
CE8
PEB 2254
(5A)
(5B)
11.96