PEB2254H-V14 Infineon Technologies, PEB2254H-V14 Datasheet - Page 283

• Manufacturer Part Number: PEB2254H-V14
• Manufacturer: Infineon Technologies

Specifications of PEB2254H-V14

• Operating Supply Voltage (typ): 5V
• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Compliant

XLSC…
XPR…
Interrupt Status Register 2 (Read)
ISR2
All bits are reset when ISR2 is read.
If bit IPC.VIS is set to ‘1’, interrupt statuses in ISR2 may be flagged although they are
masked via register IMR2. However, these masked interrupt statuses neither generate a
signal on INT, nor are visible in register GIS.
FAR…
LFA…
MFAR…
Semiconductor Group
7
FAR
Transmit Line Status Change
XLSC is set to one with the rising edge of the bit FRS1.XLO or with
any change of bit FRS1.XLS.
The actual status of the transmit line monitor can be read from the
FRS1.XLS and FRS1.XLO.
Transmit Pool Ready
A data block of up to 32 bytes can be written to the transmit FIFO.
XPR enables the fastest access to XFIFO. It has to be used for
transmission of long frames, back-to-back frames or frames with
shared flags.
Frame Alignment Recovery
The framer has reached synchronization. Set with the falling edge of
bit FSR0.LFA.
It is set also after alarm simulation is finished and the receiver is still
synchron.
Loss of Frame Alignment
The framer has lost synchronization and bit FRS0.LFA is set.
It will be set during alarm simulation.
Multiframe Alignment Recovery
Set when the framer has reached multiframe alignment in F12 or F72
format. With the negative transition of bit FRS0.LMFA this bit will be
set. It will be set during alarm simulation.
LFA
MFAR
LMFA
283
AIS
LOS
Operational Description T1
RAR
0
RA
PEB 2254
(6A)
11.96