UPD78F0890GK(A)-GAJ-AX NEC, UPD78F0890GK(A)-GAJ-AX Datasheet - Page 131

• Manufacturer Part Number: UPD78F0890GK(A)-GAJ-AX
• Description: 8BIT MCU, 128K FLASH, 7K RAM, LQFP
• Manufacturer: NEC

Specifications of UPD78F0890GK(A)-GAJ-AX

• Controller Family/series: UPD78F
• No. Of I/o's: 55
• Ram Memory Size: 7KB
• Cpu Speed: 20MHz
• No. Of Timers: 10
• No. Of Pwm: RoHS Compliant
• Core Size: 8bit
• Program Memory Size: 128KB
• Oscillator Type: External, Internal

(3) Main clock mode register (MCM)
This register selects the main system clock supplied to CPU clock and clock supplied to peripheral hardware
clock.
MCM can be set by a 1-bit or 8-bit memory manipulation instruction.
Reset signal generation clears this register to 00H.
Address: FFA1H
Symbol
MCM
Note Bit 1 is read-only.
Cautions 1. XSEL can be changed only once after a reset release.
XSEL
MCS
7
0
0
0
1
1
0
1
After reset: 00H
2. The peripheral hardware cannot operate when the peripheral hardware clock is
3. A clock other than f
4. It takes one clock to change the CPU clock.
Figure 6-4. Format of Main Clock Mode Register (MCM)
Operates with internal high-speed oscillation clock
Operates with high-speed system clock
stopped.
peripheral hardware clock has been stopped, initialize the peripheral hardware.
regardless of the setting of XSEL and MCM0.
• Watchdog timer
• When “f
• Peripheral hardware selects the external clock as the clock source
MCM0
(Except when the external count clock of TM0n (n = 0, 1) is selected (TI00n pin
valid edge))
6
0
0
1
0
1
R/W
CHAPTER 6 CLOCK GENERATOR
Internal high-speed oscillation clock
(f
High-speed system clock (f
RL
RH
To resume the operation of the peripheral hardware after the
/2
Selection of clock supplied to main system clock and peripheral hardware
)
Note
7
User’s Manual U17554EJ4V0UD
5
0
” is selected as the count clock for 8-bit timer H1
Main system clock (f
PRS
4
0
Main system clock status
is supplied to the following peripheral functions
XH
XP
)
)
3
0
Internal high-speed oscillation clock
(f
High-speed system clock (f
RH
XSEL
Peripheral hardware clock (f
)
<2>
MCS
<1>
XH
)
MCM0
<0>
PRS
)
131