UPD78F0890GK(A)-GAJ-AX NEC, UPD78F0890GK(A)-GAJ-AX Datasheet - Page 565

• Manufacturer Part Number: UPD78F0890GK(A)-GAJ-AX
• Description: 8BIT MCU, 128K FLASH, 7K RAM, LQFP
• Manufacturer: NEC

Specifications of UPD78F0890GK(A)-GAJ-AX

• Controller Family/series: UPD78F
• No. Of I/o's: 55
• Ram Memory Size: 7KB
• Cpu Speed: 20MHz
• No. Of Timers: 10
• No. Of Pwm: RoHS Compliant
• Core Size: 8bit
• Program Memory Size: 128KB
• Oscillator Type: External, Internal

Cautions 1. Do not change the value of MDB0 during operation processing (while bit 7 (DMUE) of
(3) Multiplication/division data register B0 (MDB0)
Address: FFAEH, FFAFH
Symbol
MDB0
The functions of MDA0 when an operation is executed are shown in the table below.
The register configuration differs between when multiplication is executed and when division is executed, as
follows.
• Register configuration during multiplication
• Register configuration during division
MDA0 fetches the calculation result as soon as the clock is input, when bit 7 (DMUE) of multiplier/divider
control register 0 (DMUC0) is set to 1.
MDA0H and MDA0L can be set by an 8-bit or 16-bit memory manipulation instruction.
Reset signal generation clears MDA0H and MDA0L to 0000H.
MDB0 is a register that stores a 16-bit multiplier B in the multiplication mode and a 16-bit divisor in the
division mode.
MDB0 can be set by an 8-bit or 16-bit memory manipulation instruction.
Reset signal generation clears MDB0 to 0000H.
MDA0 (bits 15 to 0) × MDB0 (bits 15 to 0) = MDA0 (bits 31 to 0)
MDA0 (bits 31 to 0) ÷ MDB0 (bits 15 to 0) = MDA0 (bits 31 to 0) … SDR0 (bits 15 to 0)
DMUSEL0
2. Do not clear MDB0 to 0000H in the division mode. If set, undefined operation results are
<Multiplier A>
<Dividend>
MDB
015
0
1
multiplier/divider control register 0 (DMUC0) is 1).
executed, but the result is undefined.
stored in MDA0 and SDR0.
Figure 20-4. Format of Multiplication/Division Data Register B0 (MDB0)
MDB
014
Table 20-2. Functions of MDA0 During Operation Execution
MDB
013
Division mode
Multiplication mode
After reset: 0000H
FFAFH (MDB0H)
<Multiplier B>
<Divisor>
MDB
012
Operation Mode
CHAPTER 20 MULTIPLIER/DIVIDER
MDB
011
User’s Manual U17554EJ4V0UD
MDB
010
R/W
MDB
009
<Product>
<Quotient>
MDB
Dividend
Higher 16 bits: 0, Lower 16
bits: Multiplier A
008
MDB
007
Setting
MDB
006
Even in this case, the operation is
<Remainder>
MDB
005
FFAEH (MDB0L)
MDB
004
Division result (quotient)
Multiplication result
(product)
MDB
003
Operation Result
MDB
002
MDB
001
MDB
000
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