UPD78F0890GK(A)-GAJ-AX NEC, UPD78F0890GK(A)-GAJ-AX Datasheet - Page 320

• Manufacturer Part Number: UPD78F0890GK(A)-GAJ-AX
• Description: 8BIT MCU, 128K FLASH, 7K RAM, LQFP
• Manufacturer: NEC

Specifications of UPD78F0890GK(A)-GAJ-AX

• Controller Family/series: UPD78F
• No. Of I/o's: 55
• Ram Memory Size: 7KB
• Cpu Speed: 20MHz
• No. Of Timers: 10
• No. Of Pwm: RoHS Compliant
• Core Size: 8bit
• Program Memory Size: 128KB
• Oscillator Type: External, Internal

320
Note If “reception as 0 parity” is selected, the parity is not judged. Therefore, bit 2 (PE61) of asynchronous serial
Cautions 1.
Figure 14-8. Format of Asynchronous Serial Interface Operation Mode Register 61 (ASIM61) (2/2)
interface reception error status register 61 (ASIS61) is not set and the error interrupt does not occur.
2.
3.
4.
5.
6.
7.
8.
9.
ISRM61
PS611
CL61
SL61
To start the transmission, set POWER61 to 1 and then set TXE61 to 1. To stop the
transmission, clear TXE61 to 0, and then clear POWER61 to 0.
To start the reception, set POWER61 to 1 and then set RXE61 to 1. To stop the reception,
clear RXE61 to 0, and then clear POWER61 to 0.
Set POWER61 to 1 and then set RXE61 to 1 while a high level is input to the RxD61 pins. If
POWER61 is set to 1 and RXE61 is set to 1 while a low level is input, reception is started.
TXE61 and RXE61 are synchronized by the base clock (f
transmission or reception again, set TXE61 or RXE61 to 1 at least two clocks of the base
clock after TXE61 or RXE61 has been cleared to 0. If TXE61 or RXE61 is set within two clocks
of the base clock, the transmission circuit or reception circuit may not be initialized.
Set transmit data to TXB61 at least one base clock (f
Clear the TXE61 and RXE61 bits to 0 before rewriting the PS611, PS601, and CL61 bits.
Fix the PS611 and PS601 bits to 0 when used in LIN communication operation.
Clear TXE61 to 0 before rewriting the SL61 bit. Reception is always performed with “the
number of stop bits = 1”, and therefore, is not affected by the set value of the SL61 bit.
Make sure that RXE61 = 0 when rewriting the ISRM61 bit.
0
0
1
1
0
1
0
1
0
1
Character length of data = 7 bits
Character length of data = 8 bits
Number of stop bits = 1
Number of stop bits = 2
“INTSRE61” occurs in case of error (at this time, INTSR61 does not occur).
“INTSR61” occurs in case of error (at this time, INTSRE61 does not occur).
PS601
CHAPTER 14 SERIAL INTERFACES UART60 AND UART61
0
1
0
1
Enables/disables occurrence of reception completion interrupt in case of error
Does not output parity bit.
Outputs 0 parity.
Outputs odd parity.
Outputs even parity.
User’s Manual U17554EJ4V0UD
Transmission operation
Specifies character length of transmit/receive data
Specifies number of stop bits of transmit data
XCLK6
) after setting TXE61 = 1.
Reception without parity
Reception as 0 parity
Judges as odd parity.
Judges as even parity.
XCLK6
) set by CKSR61. To enable
Reception operation
Note