UPD78F0890GK(A)-GAJ-AX NEC, UPD78F0890GK(A)-GAJ-AX Datasheet - Page 233

• Manufacturer Part Number: UPD78F0890GK(A)-GAJ-AX
• Description: 8BIT MCU, 128K FLASH, 7K RAM, LQFP
• Manufacturer: NEC

Specifications of UPD78F0890GK(A)-GAJ-AX

• Controller Family/series: UPD78F
• No. Of I/o's: 55
• Ram Memory Size: 7KB
• Cpu Speed: 20MHz
• No. Of Timers: 10
• No. Of Pwm: RoHS Compliant
• Core Size: 8bit
• Program Memory Size: 128KB
• Oscillator Type: External, Internal

8.4.2 Operation as external event counter
counter 5n (TM5n).
Either the rising or falling edge can be selected.
and an interrupt request signal (INTTM5n) is generated.
The external event counter counts the number of external clock pulses to be input to the TI5n pin by 8-bit timer
TM5n is incremented each time the valid edge specified by timer clock selection register 5n (TCL5n) is input.
When the TM5n count value matches the value of 8-bit timer compare register 5n (CR5n), TM5n is cleared to 0
Whenever the TM5n value matches the value of CR5n, INTTM5n is generated.
<1> Set each register.
<2> When TCE5n = 1 is set, the number of pulses input from the TI5n pin is counted.
<3> When the values of TM5n and CR5n match, INTTM5n is generated (TM5n is cleared to 00H).
<4> After these settings, INTTM5n is generated each time the values of TM5n and CR5n match.
Setting
TM5n count value
Note 8-bit timer/event counter 50: PM17
• Set the port mode register (PM17 or PM33)
• TCL5n: Select TI5n pin input edge.
• CR5n:
• TMC5n: Stop the count operation, select the mode in which clear & start occurs on match of TM5n and
Remark N = 00H to FFH
8-bit timer/event counter 51: PM33
INTTM5n
Figure 8-12. External Event Counter Operation Timing (with Rising Edge Specified)
CR5n
TI5n
n = 0, 1
TI5n pin falling edge → TCL5n = 00H
TI5n pin rising edge → TCL5n = 01H
Compare value
CR5n, disable the timer F/F inversion operation, disable timer output.
(TMC5n = 0000××00B × = Don’t care)
Count start
00
CHAPTER 8 8-BIT TIMER/EVENT COUNTERS 50 AND 51
01
02
03
User’s Manual U17554EJ4V0UD
04
Note
05
to 1.
N – 1
N
N
00
01
02
03
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