UPD78F0890GK(A)-GAJ-AX NEC, UPD78F0890GK(A)-GAJ-AX Datasheet - Page 434

8BIT MCU, 128K FLASH, 7K RAM, LQFP

UPD78F0890GK(A)-GAJ-AX

Manufacturer Part Number
UPD78F0890GK(A)-GAJ-AX
Description
8BIT MCU, 128K FLASH, 7K RAM, LQFP
Manufacturer
NEC
Datasheet

Specifications of UPD78F0890GK(A)-GAJ-AX

Controller Family/series
UPD78F
No. Of I/o's
55
Ram Memory Size
7KB
Cpu Speed
20MHz
No. Of Timers
10
No. Of Pwm
RoHS Compliant
Core Size
8bit
Program Memory Size
128KB
Oscillator Type
External, Internal
434
(9) CAN module error counter register (C0ERC)
Remark REC6 to REC0 of the reception error counter are invalid in the reception error passive
Remark TEC7 to TEC0 of the transmission error counter are invalid in the bus-off state (BOFF = 1).
After reset: 0000H
The C0ERC register indicates the count value of the transmission/reception error counter.
REPS
0
1
REC6-REC0
C0ERC
TEC7-TEC0
0-127
0-255
state (RECS [1:0] = 11B).
Reception error counter is not error passive (<128)
Reception error counter is error passive range (≥128)
REPS
TEC7
15
7
Number of reception errors. These bits reflect the status of the reception error
counter. The number of errors is defined by the CAN protocol.
Number of transmission errors. These bits reflect the status of the transmission error
counter. The number of errors is defined by the CAN protocol.
R
REC6
TEC6
14
6
CHAPTER 16 CAN CONTROLLER
Address: FF94H, FF95H
REC5
TEC5
13
User’s Manual U17554EJ4V0UD
5
Reception error passive status bit
REC4
TEC4
12
Transmission Error Counter Bit
4
Reception Error Counter Bit
REC3
TEC3
11
3
REC2
TEC2
10
2
REC1
TEC1
9
1
REC0
TEC0
8
0

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